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MDD(Microdiode Semiconductor) 74LVC244APW product image
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MDD(Microdiode Semiconductor) 74LVC244APWRoHS

Manufacturer
MPN
74LVC244APW
LCSC Part #
C53552925
Packaging
TSSOP-20
Customer #
Key Attributes
Schmitt trigger 1.65V~5.5V 8 1 20uA 15ns@5.5V,15pF TSSOP-20 Buffers, Drivers, Receivers, Transceivers RoHS
Datasheetpdf iconMDD(Microdiode Semiconductor) 74LVC244APW
In-Stock: 3,795
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QtyUnit PriceTotal Amount
5+$ 0.1886$ 0.94
50+$ 0.1492$ 7.46
150+$ 0.1323$ 19.85
500+$ 0.1113$ 55.65
2,500+$ 0.1019$ 254.75
5,000+$ 0.0962$ 481.00
Standard Packaging2500/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers
ManufacturerMDD(Microdiode Semiconductor)
PackagingTSSOP-20
Current - Output High(IOH)32mA
Input typeSchmitt trigger
Series74LVC
Voltage - Supply1.65V~5.5V
Operating Temperature-40℃~+125℃
Output TypeTri-State
Current - Output Low(IOL)32mA
Number of Bits per Element8
Channel TypeUnidirectional
Number of Elements1
Quiescent Current20uA
Propagation Delay15ns@5.5V,15pF

Additional Information

TypeDetails
Minimum5
Multiple5
Standard Packaging2500
Sales UnitPiece

Introduction

AI Translation

The 74LVC244A and 74LVCH244A are 8-bit buffers/line drivers with 3-state outputs. These devices can be used as two 4-bit buffers or one 8-bit buffer. Both devices feature two output enable inputs (1OE and 2OE), each controlling four 3-state outputs. When nOE is HIGH, the outputs are in a high-impedance off-state. Inputs can be driven by 3.3V or 5V devices. This feature allows these devices to be used as translators in mixed 3.3V and 5V environments. All inputs incorporate Schmitt-trigger action, allowing the circuit to accommodate slower input rise and fall times. The device is fully specified for partial power-down applications using IOFF. The IOFF circuit disables the outputs, preventing potentially damaging backflow current through the device when it is powered down.

Features

AI Translation
  • Wide supply voltage range: 1.2V to 5.5V
  • Direct TTL-level interface compatible
  • CMOS low power consumption
  • Input overvoltage tolerance up to 5.5V
  • Bus-hold on all data inputs (74LVCH244A only)
  • IOFF circuitry for partial power-down operation
  • Latch-up performance exceeds 250mA
  • JEDEC standard compliant:
    • JESD8-7A (1.65V to 1.95V)
    • JESD8-5A (2.3V to 2.7V)
    • JESD8-C/JESD36 (2.7V to 3.6V)
  • ESD protection:
    • HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 6000V
    • CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000V