LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
Cart
HGSEMI CD4078BE product image
  • CD4078BE thumbnail 1
  • CD4078BE thumbnail 2
  • CD4078BE thumbnail 3
  • Pinout
  • Footprint
Images for reference only

HGSEMI CD4078BERoHS

Manufacturer
HGSEMIAsian Brands
MPN
CD4078BE
LCSC Part #
C3007970
Packaging
DIP-14
Customer #
Key Attributes
CMOS 8-Input NOR/OR High-Voltage Types
Datasheetpdf iconHGSEMI CD4078BE
In-Stock: 545
545 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
5+$ 0.201$ 1.01
50+$ 0.1483$ 7.42
150+$ 0.131$ 19.65
500+$ 0.1093$ 54.65
2,000+$ 0.0996$ 199.20
5,000+$ 0.0938$ 469.00
Standard Packaging25/Full Tube
Better price for more quantity?
$

Products Specifications

Show similar products (0) >
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters
ManufacturerHGSEMI
PackagingDIP-14
Features-
Input Logic Level - High3.5V;7V;11V
Input Logic Level - Low1.5V;3V;4V
Operating Temperature-40℃~+85℃
Logic Family4000 Series
Output Logic Level - High4.95V;9.95V;14.95V
Quiescent Current(Iq)5uA
Voltage - Supply5V~18V
Current - Output High(IOH)6.8mA
Number of Channels1;8
Output Logic Level - Low50mV
Propagation Delay110ns@15V,50pF
Current - Output Low(IOL)6.8mA
Report an ErrorShow similar products (0) >

Additional Information

TypeDetails
Minimum5
Multiple5
Standard Packaging25
Sales UnitPiece

Introduction

AI Translation

CD4078B NOR/OR Gate provides the system designer with direct implementa-tion of the positivelogic 8-input NOR and OR functions and supplements the existing family of CMOS gates. The CD4078B types are supplied in 14-lead dual-in-line plastic packages (N suffix), 14-lead small-outline packages (M suffixes) and 14 lead thin shrink small-outline packages (MT suffixes).

Features

AI Translation
  • Medium-Speed Operation: tPHL, tPLH = 75ns(typ.) at VDD = 10V
  • Buffered inputs and output
  • 5V, 10V and 15V parametric ratings
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20V
  • Maximum input current of 1uA at 18V over full package-temperature range; 100nA at 18V and 25°C
  • Noise margin (over full package-temperature range): 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
  • Meets all requirements of JEDEC Tentative Standard No. 13B “Standard Specifications for Description of B Series CMOS Devices”