Nexperia 74LVC2G32GF,115
| Manufacturer | |
| MPN | 74LVC2G32GF,115 |
| LCSC Part # | C548637 |
| Packaging | XSON-8(1x1.4) |
| Customer # | |
| Key Attributes | 4uA 1.65V~5.5V XSON-8(1x1.4) Gates and Inverters RoHS |
| Datasheet |  Nexperia 74LVC2G32GF,115 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | Nexperia | |
| Packaging | XSON-8(1x1.4) | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Input Logic Level - Low | 700mV;800mV | |
| Operating Temperature | -40℃~+125℃ | |
| Input Logic Level - High | 1.7V;2V | |
| Logic Family | 74LVC | |
| Output Logic Level - High | 2.3V;3.8V | |
| Quiescent Current(Iq) | 4uA | |
| Voltage - Supply | 1.65V~5.5V | |
| Current - Output High(IOH) | 24mA | |
| Number of Channels | 2;2 | |
| Propagation Delay | - | |
| Output Logic Level - Low | 550mV;800mV | |
| Current - Output Low(IOL) | 24mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 5000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC2G32 is a dual 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features
- Wide supply voltage range from 1.65 V to 5.5 V
- Overvoltage tolerant inputs to 5.5 V
- High noise immunity
- CMOS low power dissipation
- 5 V tolerant outputs in the Power-down mode
- ±24 mA output drive (VCC = 3.0 V)
- Latch-up performance exceeds 250 mA
- Direct interface with TTL levels
- IOFF circuitry provides partial Power-down mode operation
- Complies with JEDEC standard: JESD8 - 7 (1.65 V to 1.95 V) JESD8 - 5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS - 001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS - 002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | Nexperia | |
| Packaging | XSON-8(1x1.4) | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Input Logic Level - Low | 700mV;800mV | |
| Operating Temperature | -40℃~+125℃ | |
| Input Logic Level - High | 1.7V;2V | |
| Logic Family | 74LVC | |
| Output Logic Level - High | 2.3V;3.8V | |
| Quiescent Current(Iq) | 4uA | |
| Voltage - Supply | 1.65V~5.5V | |
| Current - Output High(IOH) | 24mA | |
| Number of Channels | 2;2 | |
| Propagation Delay | - | |
| Output Logic Level - Low | 550mV;800mV | |
| Current - Output Low(IOL) | 24mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 5000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC2G32 is a dual 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features
- Wide supply voltage range from 1.65 V to 5.5 V
- Overvoltage tolerant inputs to 5.5 V
- High noise immunity
- CMOS low power dissipation
- 5 V tolerant outputs in the Power-down mode
- ±24 mA output drive (VCC = 3.0 V)
- Latch-up performance exceeds 250 mA
- Direct interface with TTL levels
- IOFF circuitry provides partial Power-down mode operation
- Complies with JEDEC standard: JESD8 - 7 (1.65 V to 1.95 V) JESD8 - 5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS - 001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS - 002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |