WCH CH32V103C8T6

QingKe V3 series microprocessors are self-developed 32-bit general-purpose MCU microprocessors based on standard RISC-V instruction set architecture. This series includes V3A, V3B and V3C, of which V3A supports RV32IMAC standard instruction set extension and V3B/C supports RV32IMCB standard instruction set extension and customized instruction set extension XW. Both of them support single-cycle multiplication and hardware division, in addition to hardware pressure stack (HPE), table-free interrupt (VTF), streamlined 1- and 2-wire debugging interfaces, "WFE" instructions and other special features. In addition, it also supports Hardware Prologue/Epilogue (HPE), Vector Table Free (VTF), streamlined 1-/2-wire debugging interface, and support for "WFE" instruction.

• ISA：RV32IM[A]C[B]
• Pipeline：3
• FPU：Not supported
• Branch prediction：Static branch prediction
• Interrupt：Support a total of 256 interrupts including exceptions, and supports VTF
• HPE：Support 2 levels of HPE
• Physical Memory Protection (PMP)：Supported
• Low-power consumption mode：Support Sleep and Deep sleep modes, and support WFI and WFE sleep methods
• Extended Instruction Set：Supported
• Debug：1/2-wire SDI, standard RISC-V debug