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Infineon CY7C429-15JXCT product image
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Infineon CY7C429-15JXCTRoHS

Manufacturer
MPN
CY7C429-15JXCT
LCSC Part #
C19178070
Packaging
PLCC-32(11.4x14)
Customer #
Key Attributes
PLCC-32(11.4x14) FIFOs Memory RoHS
Datasheetpdf iconInfineon CY7C429-15JXCT
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/FIFOs Memory
ManufacturerInfineon
PackagingPLCC-32(11.4x14)
FeaturesAutomatic retransmission function;Output enable

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging86
Sales UnitPiece

Introduction

AI Translation

CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and CY7C432/3 are first-in first-out (FIFO) memories available in 600-mil wide and 300-mil wide packages. They are organized as 256, 512, 1024, 2048, and 4096 words, respectively, each 9 bits wide. Each FIFO memory is organized so that data is read out in the same order it was written in. Full and empty flags are provided to prevent overflow and underflow. Three additional pins are provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique routes control signals from one device to another in parallel, eliminating the serial accumulation of propagation delays and thus maintaining full throughput. Data is routed in a similar manner.

Read and write operations may be asynchronous; the rate for each operation can reach 50.0 MHz. A write operation occurs when the write signal (W̄) is LOW. A read operation occurs when the read signal (R̄) is LOW. When R̄ is HIGH, the nine data outputs enter a high-impedance state.

A half-full (HF) output flag is provided, which is valid in stand-alone and width expansion configurations. In the depth expansion configuration, this pin provides expansion output (XO) information to signal the next FIFO that it will be activated.

In stand-alone and width expansion configurations, asserting the retransmit (RT) input LOW causes the FIFO to retransmit data. During retransmission, both the read enable (R) and write enable (W) must be HIGH, after which R is used to access the data.

CY7C419, CY7C420, CY7C421, CY7C424, CY7C425, CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated using advanced 0.65-micron P-well CMOS technology. Input ESD protection exceeds 2000V, and latch-up is prevented through careful layout and guard rings.

Features

AI Translation
  • Asynchronous FIFO buffer memory
  • 256 × 9 (CY7C419)
  • 512 × 9 (CY7C421)
  • 1K × 9 (CY7C425)
  • 2K × 9 (CY7C429)
  • 4K × 9 (CY7C433)
  • Dual-port RAM cell
  • High-speed 50.0 MHz read/write, independent of depth/width
  • Low operating power: ICC = 35 mA
  • Empty and full flags (half-full flag in independent mode)
  • TTL compatible
  • Retransmit capability in independent mode
  • Width expandable
  • PLCC, 7x7 TQFP, SOJ, 300-mil and 600-mil DIP packages
  • Lead-free packages available
  • Pin compatible and functionally equivalent to IDT7200, IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201, AM7202, AM7203, and AM7204