Rayson RS512M16Z2DD-62DT

Products Specifications

Type	Description	All
Category	Integrated Circuits (ICs)/Memory/Memory (ICs)
Manufacturer	Rayson
Packaging	FBGA-96(7.5x13)
Refresh Current	-
Voltage - Supply	1.14V~1.26V;2.375V~2.75V
Memory Size	8Gbit
Operating temperature	0℃~+95℃
Clock Frequency	1.6GHz
Features	Auto self-refresh;Auto precharge function;Asynchronous reset function;Data mask function;CRC function;Dynamic on-chip termination;ZQ calibration function;Write leveling function
Memory Format	DDR4 SDRAM
Current - Supply	-

AI Translation

VDD = VDDQ = 1.2V ± 60mV
VPP = 2.5V, -125mV/+250mV
On-die, internal, adjustable VREFDQ generation
1.2V pseudo open-drain I/O
TC of 0°C to 95°C – 64ms, 8192-cycle refresh at 0°C to 85°C – -32ms at 85°C to 95°C
16 internal banks (x4, x8): 4 groups of 4 banks each
8 internal banks (x16): 2 groups of 4 banks each
8n-bit prefetch architecture
Programmable data strobe preambles
Data strobe preamble training
Command/Address latency (CAL)
Multipurpose register READ and WRITE capability
Write and read leveling
Self refresh mode
Low-power auto self refresh (LPASR)
Temperature controlled refresh (TCR)
Fine granularity refresh
Self refresh abort
Maximum power saving
Output driver calibration
Nominal, park, and dynamic on-die termination (ODT)
Data bus inversion (DBI) for data bus
Command/Address (CA) parity
Databus write cyclic redundancy check (CRC)
Per-DRAM addressability
Connectivity test (x16)
Post package repair (PPR) and soft post package repair (sPPR) capability
JEDEC JESD-79-4 compliant

In-Stock: 80

80 In stock, ships now

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Qty	Unit Price	Total Amount
1+	$ 35.9999	$ 36.00
30+	$ 34.202	$ 1026.06
Standard Packaging500/Full Reel

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Type	Description	All
Category	Integrated Circuits (ICs)/Memory/Memory (ICs)
Manufacturer	Rayson
Packaging	FBGA-96(7.5x13)
Refresh Current	-
Voltage - Supply	1.14V~1.26V;2.375V~2.75V
Memory Size	8Gbit
Operating temperature	0℃~+95℃
Clock Frequency	1.6GHz
Features	Auto self-refresh;Auto precharge function;Asynchronous reset function;Data mask function;CRC function;Dynamic on-chip termination;ZQ calibration function;Write leveling function
Memory Format	DDR4 SDRAM
Current - Supply	-

AI Translation

VDD = VDDQ = 1.2V ± 60mV
VPP = 2.5V, -125mV/+250mV
On-die, internal, adjustable VREFDQ generation
1.2V pseudo open-drain I/O
TC of 0°C to 95°C – 64ms, 8192-cycle refresh at 0°C to 85°C – -32ms at 85°C to 95°C
16 internal banks (x4, x8): 4 groups of 4 banks each
8 internal banks (x16): 2 groups of 4 banks each
8n-bit prefetch architecture
Programmable data strobe preambles
Data strobe preamble training
Command/Address latency (CAL)
Multipurpose register READ and WRITE capability
Write and read leveling
Self refresh mode
Low-power auto self refresh (LPASR)
Temperature controlled refresh (TCR)
Fine granularity refresh
Self refresh abort
Maximum power saving
Output driver calibration
Nominal, park, and dynamic on-die termination (ODT)
Data bus inversion (DBI) for data bus
Command/Address (CA) parity
Databus write cyclic redundancy check (CRC)
Per-DRAM addressability
Connectivity test (x16)
Post package repair (PPR) and soft post package repair (sPPR) capability
JEDEC JESD-79-4 compliant