SONIX SN8P2602C
| Manufacturer | SONIXAsian Brands |
| MPN | SN8P2602C |
| LCSC Part # | C85339 |
| Packaging | SOP-18-300mil |
| Customer # | |
| Key Attributes | 16 SOP-18-300mil Microcontrollers RoHS |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | SONIX | |
| Packaging | SOP-18-300mil | |
| Program Memory Type | OTP | |
| Voltage - Supply | 2.2V~5.5V | |
| Program Storage Size | 1KB | |
| CPU Core | - | |
| Number of I/O | 16 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 40 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Memory configuration ROM: 1κ * 16-bit. RAM: 48 * 8-bit.
- Fcpu (instruction cycle): Fcpu = Fosc/1, Fosc/2, Fosc/4, Fosc/8, Fosc/16, Fosc/32, Fosc/64, Fosc/128.
- 3 interrupt sources: 2 internal interrupts (T0, TC0), 1 external interrupt (INT0).
- 1 8-bit basic timer T0 with RTC function (0.5S).
- 1 8-bit timer TC0 with external event counter, Buzzer, and PWM functions.
- 1-channel 2K/4K buzzer output.
- Built-in watchdog timer, clock source supplied by low-speed RC clock (16KHz @3V, 32KHz @5V).
- I/O pin configuration: bidirectional I/O ports P0, P1, P5; unidirectional input pin P1.5; ports with pull-up resistors P0, P1, P5; pins with pull-down resistors P5.0~P5.3; ports with wake-up function P0, P1 level transition; 40mA sink pins P5.0~P5.3, P5.5; programmable open-drain pin P1.0; external interrupt trigger edge P0.0, controlled by PEDGE register.
- 4 system clocks: external high-speed clock (RC clock, up to 10MHz; crystal clock, up to 16MHz); internal high-speed clock (RC clock, up to 16MHz); internal low-speed clock (RC clock, 16KHz (3V), 32KHz (5V)).
- 4 operating modes: 3-level LVD reset system monitoring supply voltage. Normal mode — both high- and low-speed clocks operate; low-speed clock mode — only low-speed clock operates; sleep mode — both high- and low-speed clocks halted; green mode — periodic wake-up by timer. Instruction length is 1 word; most instructions require only one cycle; JMP/CALL instructions can address the entire ROM space; table lookup instruction MOVC can address the entire ROM space.
- Package types: DIP 18 pin, SOP 18 pin, SSOP 20 pin.
Not available now
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | SONIX | |
| Packaging | SOP-18-300mil | |
| Program Memory Type | OTP | |
| Voltage - Supply | 2.2V~5.5V | |
| Program Storage Size | 1KB | |
| CPU Core | - | |
| Number of I/O | 16 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 40 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Memory configuration ROM: 1κ * 16-bit. RAM: 48 * 8-bit.
- Fcpu (instruction cycle): Fcpu = Fosc/1, Fosc/2, Fosc/4, Fosc/8, Fosc/16, Fosc/32, Fosc/64, Fosc/128.
- 3 interrupt sources: 2 internal interrupts (T0, TC0), 1 external interrupt (INT0).
- 1 8-bit basic timer T0 with RTC function (0.5S).
- 1 8-bit timer TC0 with external event counter, Buzzer, and PWM functions.
- 1-channel 2K/4K buzzer output.
- Built-in watchdog timer, clock source supplied by low-speed RC clock (16KHz @3V, 32KHz @5V).
- I/O pin configuration: bidirectional I/O ports P0, P1, P5; unidirectional input pin P1.5; ports with pull-up resistors P0, P1, P5; pins with pull-down resistors P5.0~P5.3; ports with wake-up function P0, P1 level transition; 40mA sink pins P5.0~P5.3, P5.5; programmable open-drain pin P1.0; external interrupt trigger edge P0.0, controlled by PEDGE register.
- 4 system clocks: external high-speed clock (RC clock, up to 10MHz; crystal clock, up to 16MHz); internal high-speed clock (RC clock, up to 16MHz); internal low-speed clock (RC clock, 16KHz (3V), 32KHz (5V)).
- 4 operating modes: 3-level LVD reset system monitoring supply voltage. Normal mode — both high- and low-speed clocks operate; low-speed clock mode — only low-speed clock operates; sleep mode — both high- and low-speed clocks halted; green mode — periodic wake-up by timer. Instruction length is 1 word; most instructions require only one cycle; JMP/CALL instructions can address the entire ROM space; table lookup instruction MOVC can address the entire ROM space.
- Package types: DIP 18 pin, SOP 18 pin, SSOP 20 pin.
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |


