- Pinout Diagram
- Footprint Diagram
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EDA ModelsEasyEDA
STC Micro STC15W401AS-35C-SOP16
| Manufacturer | STC MicroAsian Brands |
| MPN | STC15W401AS-35C-SOP16 |
| LCSC Part # | C65499 |
| Packaging | SOP-16 |
| Customer # | |
| Key Attributes | SOP-16 Microcontrollers RoHS |
| Datasheet |  STC Micro STC15W401AS-35C-SOP16 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | STC Micro | |
| Packaging | SOP-16 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 50 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Ultra-strong anti-interference, undecipherable
- STC 8th-generation encryption technology
- No external crystal oscillator or external reset required
- External EEPROM can be eliminated via IAP technology
- ISP/IAP, in-system programming, no programmer/emulator required
- Large 2K-byte SRAM
- Dual UART, two independent serial ports
- High-speed 10-bit ADC, 8 channels
- 1 clock/machine cycle 8051
- High-speed, high-reliability
- Ultra-low power consumption, ultra-low cost
- Ultra-strong ESD protection
- Large 4096-byte on-chip RAM data memory
- Wide voltage range: 2.5V～5.5V
- Low-power design: slow-speed mode, idle mode, power-down mode (wake-up via external interrupt or internal power-down wake-up timer)
- 16 selectable reset threshold voltages during ISP programming, built-in high-reliability reset circuit
- Internal clock configurable from 5MHz~30MHz during ISP programming (equivalent to standard 8051: 60～360MHz), internal high-precision R/C clock (±0.3%), ±1% temperature drift (-40℃~+85℃), ±0.6% temperature drift at room temperature (-20℃~+65℃)
- Power-down wake-up sources: INT0/INT1 (rising/falling edge interrupt), INT2/INT3/INT4 (falling edge interrupt); CCP0/CCP1/RxD/RxD2/RxD3/RxD4/T0/T1/T2/T3/T4 pins; internal dedicated power-down wake-up timer
- 16/32/40/48/56/58K/61K/63.5K bytes on-chip Flash program memory, erase/write endurance over 100,000 cycles
- Large on-chip EEPROM, erase/write endurance over 100,000 cycles
- High-speed ADC, 8-channel 10-bit, up to 300,000 conversions/second; 8-channel PWM also usable as 8-channel DAC
- Comparator: usable as 1-channel ADC and power-down detection; supports comparison between external pin CMP+ and external pin CMP-, with interrupt generation and output on pin CMPO (configurable polarity); also supports comparison between external pin CMP+ and internal reference voltage
- 6-channel 15-bit dedicated high-precision PWM (with dead-band control) + 2-channel CCP (high-speed pulse output enables 2-channel 11~16-bit PWM) — usable as 8-channel DAC, or 2× 16-bit timers, or 2× external interrupts (rising/falling edge)
- 7 timers/counters total: 5× 16-bit auto-reload timers/counters (T0/T1/T2/T3/T4; T0 and T1 compatible with standard 8051 timers/counters), all capable of clock output; pin SysClkO can output divided system clock externally (÷1, ÷2, ÷4, or ÷16); 2-channel CCP provides 2 additional timers
- Programmable clock output (divided clock output from internal system clock or external pin clock input): T0 outputs clock on P3.5; T1 outputs clock on P3.4; T2 outputs clock on P3.0; T3 outputs clock on P0.4; T4 outputs clock on P0.6 — all 5 timers/counters support 1~65536 division output; system clock output on P5.4/SysClkO (STC15 series 8-pin MCU outputs main clock on P3.4/MCLKO)
- Ultra-high-speed quad UART: four fully independent high-speed asynchronous serial ports, time-division multiplexing supports up to 9 serial port configurations
- SPI high-speed synchronous serial communication interface
- Hardware watchdog timer (WDT)
- Advanced instruction set architecture, compatible with standard 8051 instruction set, with hardware multiply/divide instructions
- General-purpose I/O (62/46/42/38/30/26 pins); after reset: quasi-bidirectional/weak pull-up (standard 8051 I/O); four configurable modes: quasi-bidirectional/weak pull-up, strong push-pull/strong pull-up, input-only/high-impedance, open-drain; each I/O pin drive capability up to 20mA, total chip current not to exceed 120mA
- No external crystal oscillator or external reset required; supports external clock output and active-low reset signal output
- Significantly reduced EMI; internally configurable clock; 1 clock/machine cycle; supports low-frequency clock
- In-system emulation, in-system programming, no dedicated programmer or emulator required, supports remote firmware upgrade
- High-speed: 1 clock/machine cycle, enhanced 8051 core, 6~12× faster than standard 8051, also 20% faster than STC early 1T series MCUs (e.g., STC12/11/10 series)
- Wide voltage range: 5.5~2.4V
- Internal clock configurable from 5MHz~35MHz during ISP programming (equivalent to 8051: 60~420MHz), internal high-precision R/C clock (±0.3%), ±1% temperature drift (-40℃~+85℃), ±0.6% temperature drift at room temperature (-20℃~+65℃)
- Power-down wake-up sources: INT0/INT1 (rising/falling edge interrupt), INT2/INT3/INT4 (falling edge interrupt); T0/T2 pins; internal dedicated power-down wake-up timer
- 1K/2K/3K/4K/5K/7K bytes on-chip Flash program memory, erase/write endurance over 100,000 cycles
- 128-byte on-chip RAM data memory
- On-chip EEPROM, erase/write endurance over 100,000 cycles
- 2× 16-bit auto-reload timers T0/T2 with clock output capability; pin MCLKO can output divided internal main clock externally (÷1, ÷2, or ÷4)
- Programmable clock output (divided clock output from internal system clock or external pin clock input): T0 outputs clock on P3.5; T2 outputs clock on P3.0; internal main clock output on P3.4/MCLKO (STC15 series MCUs above 8-pin output main clock on P5.4/MCLKO)
- UART function implementable via [P3.0/INT4, P3.1] combined with timer
- General-purpose I/O (8 pins); after reset: quasi-bidirectional/weak pull-up
Applications
AI Translation
- Battery-powered systems such as water meters and gas meters
- Portable devices
Not available now
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | STC Micro | |
| Packaging | SOP-16 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 50 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Ultra-strong anti-interference, undecipherable
- STC 8th-generation encryption technology
- No external crystal oscillator or external reset required
- External EEPROM can be eliminated via IAP technology
- ISP/IAP, in-system programming, no programmer/emulator required
- Large 2K-byte SRAM
- Dual UART, two independent serial ports
- High-speed 10-bit ADC, 8 channels
- 1 clock/machine cycle 8051
- High-speed, high-reliability
- Ultra-low power consumption, ultra-low cost
- Ultra-strong ESD protection
- Large 4096-byte on-chip RAM data memory
- Wide voltage range: 2.5V～5.5V
- Low-power design: slow-speed mode, idle mode, power-down mode (wake-up via external interrupt or internal power-down wake-up timer)
- 16 selectable reset threshold voltages during ISP programming, built-in high-reliability reset circuit
- Internal clock configurable from 5MHz~30MHz during ISP programming (equivalent to standard 8051: 60～360MHz), internal high-precision R/C clock (±0.3%), ±1% temperature drift (-40℃~+85℃), ±0.6% temperature drift at room temperature (-20℃~+65℃)
- Power-down wake-up sources: INT0/INT1 (rising/falling edge interrupt), INT2/INT3/INT4 (falling edge interrupt); CCP0/CCP1/RxD/RxD2/RxD3/RxD4/T0/T1/T2/T3/T4 pins; internal dedicated power-down wake-up timer
- 16/32/40/48/56/58K/61K/63.5K bytes on-chip Flash program memory, erase/write endurance over 100,000 cycles
- Large on-chip EEPROM, erase/write endurance over 100,000 cycles
- High-speed ADC, 8-channel 10-bit, up to 300,000 conversions/second; 8-channel PWM also usable as 8-channel DAC
- Comparator: usable as 1-channel ADC and power-down detection; supports comparison between external pin CMP+ and external pin CMP-, with interrupt generation and output on pin CMPO (configurable polarity); also supports comparison between external pin CMP+ and internal reference voltage
- 6-channel 15-bit dedicated high-precision PWM (with dead-band control) + 2-channel CCP (high-speed pulse output enables 2-channel 11~16-bit PWM) — usable as 8-channel DAC, or 2× 16-bit timers, or 2× external interrupts (rising/falling edge)
- 7 timers/counters total: 5× 16-bit auto-reload timers/counters (T0/T1/T2/T3/T4; T0 and T1 compatible with standard 8051 timers/counters), all capable of clock output; pin SysClkO can output divided system clock externally (÷1, ÷2, ÷4, or ÷16); 2-channel CCP provides 2 additional timers
- Programmable clock output (divided clock output from internal system clock or external pin clock input): T0 outputs clock on P3.5; T1 outputs clock on P3.4; T2 outputs clock on P3.0; T3 outputs clock on P0.4; T4 outputs clock on P0.6 — all 5 timers/counters support 1~65536 division output; system clock output on P5.4/SysClkO (STC15 series 8-pin MCU outputs main clock on P3.4/MCLKO)
- Ultra-high-speed quad UART: four fully independent high-speed asynchronous serial ports, time-division multiplexing supports up to 9 serial port configurations
- SPI high-speed synchronous serial communication interface
- Hardware watchdog timer (WDT)
- Advanced instruction set architecture, compatible with standard 8051 instruction set, with hardware multiply/divide instructions
- General-purpose I/O (62/46/42/38/30/26 pins); after reset: quasi-bidirectional/weak pull-up (standard 8051 I/O); four configurable modes: quasi-bidirectional/weak pull-up, strong push-pull/strong pull-up, input-only/high-impedance, open-drain; each I/O pin drive capability up to 20mA, total chip current not to exceed 120mA
- No external crystal oscillator or external reset required; supports external clock output and active-low reset signal output
- Significantly reduced EMI; internally configurable clock; 1 clock/machine cycle; supports low-frequency clock
- In-system emulation, in-system programming, no dedicated programmer or emulator required, supports remote firmware upgrade
- High-speed: 1 clock/machine cycle, enhanced 8051 core, 6~12× faster than standard 8051, also 20% faster than STC early 1T series MCUs (e.g., STC12/11/10 series)
- Wide voltage range: 5.5~2.4V
- Internal clock configurable from 5MHz~35MHz during ISP programming (equivalent to 8051: 60~420MHz), internal high-precision R/C clock (±0.3%), ±1% temperature drift (-40℃~+85℃), ±0.6% temperature drift at room temperature (-20℃~+65℃)
- Power-down wake-up sources: INT0/INT1 (rising/falling edge interrupt), INT2/INT3/INT4 (falling edge interrupt); T0/T2 pins; internal dedicated power-down wake-up timer
- 1K/2K/3K/4K/5K/7K bytes on-chip Flash program memory, erase/write endurance over 100,000 cycles
- 128-byte on-chip RAM data memory
- On-chip EEPROM, erase/write endurance over 100,000 cycles
- 2× 16-bit auto-reload timers T0/T2 with clock output capability; pin MCLKO can output divided internal main clock externally (÷1, ÷2, or ÷4)
- Programmable clock output (divided clock output from internal system clock or external pin clock input): T0 outputs clock on P3.5; T2 outputs clock on P3.0; internal main clock output on P3.4/MCLKO (STC15 series MCUs above 8-pin output main clock on P5.4/MCLKO)
- UART function implementable via [P3.0/INT4, P3.1] combined with timer
- General-purpose I/O (8 pins); after reset: quasi-bidirectional/weak pull-up
Applications
AI Translation
- Battery-powered systems such as water meters and gas meters
- Portable devices
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |