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STC Micro STC15L104W-35I-SOP8 product image
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STC Micro STC15L104W-35I-SOP8RoHS

Manufacturer
STC MicroAsian Brands
MPN
STC15L104W-35I-SOP8
LCSC Part #
C12666
Packaging
SOIC-8
Customer #
Key Attributes
High-speed, low-power microcontroller that doesn't require an external crystal oscillator and reset
Datasheetpdf iconSTC Micro STC15L104W-35I-SOP8
In-Stock: 196
196 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 0.5699$ 0.57
10+$ 0.4706$ 4.71
30+$ 0.4283$ 12.85
100+$ 0.3761$ 37.61
500+$ 0.3534$ 176.70
1,000+$ 0.3387$ 338.70
Standard Packaging100/Full Tube
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microcontrollers
ManufacturerSTC Micro
PackagingSOIC-8
Operating Temperature-40℃~+85℃
Program Memory TypeFLASH
Voltage - Supply2.4V~3.6V
EEPROM1KB
Program Storage Size4KB
CPU Core51 Series
Core Size8 Bit
CPU Maximum Speed35MHz
Oscillator TypeBuilt-in
Number of I/O6

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging100
Sales UnitPiece

Features

AI Translation
  • Large-capacity 2K-byte SRAM
  • Dual UART, two independent serial ports
  • High-speed 10-bit ADC, 8 channels
  • 1 clock/machine cycle 8051
  • High-speed, high-reliability
  • Ultra-low power consumption, ultra-low cost
  • Ultra-strong ESD protection, ultra-strong noise immunity
  • 512-byte on-chip RAM data memory
  • High-speed: 1 clock/machine cycle, enhanced 8051 core, 7~12x faster than legacy 8051, also 20% faster than STC early 1T series MCUs (e.g. STC12/11/10 series)
  • Wide voltage range: 2.4V~5.5V
  • Low-power design: slow-speed mode, idle mode, power-down mode (wake-up via external interrupt or internal power-down wake-up timer)
  • No external reset required; 16-level reset threshold voltage selectable during ISP programming; built-in high-reliability reset circuit
  • No external crystal required; internal clock selectable from 5MHz~35MHz (equivalent to standard 8051: 60~420MHz); internal high-precision R/C clock (±0.3%); ±1% temperature drift (-40℃~+85℃); ±0.6% temperature drift at room temperature (-20℃~+65℃)
  • Power-down wake-up sources: INT0/INT1 (rising/falling edge interrupt), INT2/INT3/INT4 (falling edge interrupt); CCP0/CCP1/CCP2/RxD/T0/T2 pins; dedicated internal power-down wake-up timer
  • 4K/8K/13K/15.5K-byte on-chip Flash program memory, erase/write endurance >100,000 cycles
  • Large-capacity on-chip EEPROM, erase/write endurance >100,000 cycles
  • ISP/IAP, in-system programmable/in-application programmable, no programmer/emulator required
  • High-speed ADC, 8-channel 10-bit, up to 300,000 conversions/sec; 3 PWM channels also usable as 3 D/A outputs
  • Comparator: supports comparison between external pin CMP+ and external pin CMP-, capable of generating interrupts and output on pin CMPO (configurable polarity); also supports comparison between external pin CMP+ and internal reference voltage
  • 3-channel capture/compare unit (CCP/PCA/PWM) — also usable as 3 D/A outputs, 3 timers, or 3 external interrupts (rising/falling edge interrupt supported)
  • 5 timers: 2× 16-bit auto-reload timer/counters (T0/T2; T0 compatible with legacy 8051 timer/counter), both with programmable clock output; 3× CCP/PCA channels provide 3 additional timers
  • Programmable clock output (clock division output from internal system clock or external pin clock input): T0 outputs clock on P3.5; T2 outputs clock on P3.0; all 3 timer/counter clock outputs support 1~65536 division; internal master clock output on P5.4/MCLKO (STC15 series 8-pin MCUs output master clock on P3.4/MCLKO)
  • Hardware watchdog timer (WDT)
  • Ultra-high-speed asynchronous serial communication port/UART, time-division multiplexing supports 3 UART groups
  • SPI high-speed synchronous serial communication interface
  • Advanced instruction set architecture, compatible with standard 8051 instruction set, hardware multiply/divide instructions
  • General-purpose I/O (26/18/14 pins); quasi-bidirectional/weak pull-up after reset (legacy 8051 I/O mode); four configurable modes: quasi-bidirectional/weak pull-up, strong push-pull/strong pull-up, input-only/high-impedance, open-drain; each I/O pin drive capability up to 20mA, total chip maximum not to exceed 120mA
  • No external crystal required; built-in high-precision R/C clock (±0.3%); ±1% temperature drift (-40℃~+85℃); ±0.6% temperature drift at room temperature (-20℃~+65℃)
  • No external reset required; built-in high-reliability reset circuit; 16-level reset threshold voltage selectable during ISP programming; external reset circuit also supported
  • Unbreakable encryption, utilizing Macro Crystal 9th-generation encryption technology
  • Ultra-strong noise immunity: high ESD protection, entire system easily passes 20,000V ESD test; easily passes 4kV EFT test; wide voltage range immune to power supply fluctuation; wide temperature range, -40℃~+85℃
  • Significantly reduced EMI; internally configurable clock; 1 clock/machine cycle; low-frequency clock usable
  • Ultra-low power consumption: power-down mode <0.1µA with external interrupt wake-up; idle mode typical <1mA; normal operating mode 4mA~6mA; power-down mode wake-up via external interrupt or dedicated internal power-down wake-up timer; suitable for battery-powered systems
  • In-system emulation, in-system programmable, no dedicated programmer or emulator required, remote upgrade supported
  • 4K-byte SRAM, ultra-high-speed quad UART, 8-channel 10-bit PWM