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ADI AD9860BST product image
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ADI AD9860BSTRoHS

Manufacturer
MPN
AD9860BST
LCSC Part #
C7457129
Packaging
LQFP-128(14x20)
Customer #
Key Attributes
LQFP-128(14x20) RF Front End (LNA + PA) RoHS
Datasheetpdf iconADI AD9860BST

Products Specifications

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TypeDescription
CategoryRF and Wireless/RF Front End (LNA + PA)
ManufacturerADI
PackagingLQFP-128(14x20)
Features-
ApplicationsLMDS;MMDS

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging15
Sales UnitPiece

Introduction

AI Translation

The AD9860 and AD9862 are versatile integrated mixed-signal front-ends (MxFE) optimized for the broadband communications market. These devices are cost-effective mixed-signal solutions targeting wireless or wireline standard or proprietary broadband modem systems, where dynamic performance, power consumption, cost, and size are key attributes. The AD9860 features 10-bit ADCs and 12-bit DACs, while the AD9862 features 12-bit ADCs and 14-bit DACs.

The receive path (Rx) consists of two channels, each comprising a high-performance 10/12-bit 64 MSPS ADC, input buffer, programmable gain amplifier (RxPGA), digital Hilbert filter, and decimation filter. The Rx can be used to receive real, diversity, or I/Q data at baseband or low-IF. The input buffers provide a constant input impedance for both channels to simplify impedance matching with external components such as SAW filters. The RxPGA provides 20 dB of gain range for both channels. The output data bus can be multiplexed to accommodate various interface types.

The transmit path (Tx) consists of two channels, each containing a high-performance 12/14-bit 128 MSPS DAC, programmable gain amplifier (TxPGA), interpolation filter, Hilbert filter, and digital mixer for complex or real signal frequency modulation. Tx latch and demultiplexing circuitry can handle real or I/Q data. 2x and 4x interpolation rates are available to relax the requirements on external reconstruction filters. For single-channel systems, the digital Hilbert filter can be used with an external quadrature modulator to create an image-rejection architecture. The output signals from the two 12/14-bit high-performance DACs can be scaled over a 20 dB range via the TxPGA.

A programmable delay-locked loop (DLL) clock multiplier and integrated timing circuitry enable a single external reference clock or external crystal to generate clocks for all internal blocks, while also providing two external clock outputs. Additional features include a programmable sigma-delta output, four auxiliary ADC inputs, and three auxiliary DAC outputs. Device programmability is implemented via an SPI combined with a register map. The AD9860/AD9862 are housed in a space-saving 128-lead LQFP package.

Applications

AI Translation
  • Broadband wireless systems: fixed wireless, WLAN, MMDS, LMDS
  • Broadband cable systems: cable modems, VDSL, PowerPlug
  • Digital communications: set-top boxes, data modems
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