Intel/Altera EP900PC-2
| Manufacturer | |
| MPN | EP900PC-2 |
| LCSC Part # | C3291691 |
| Packaging | PDIP-40 |
| Customer # | |
| Key Attributes | EPLD PDIP-40 PLDs (Programmable Logic Device) |
| Datasheet |  Intel/Altera EP900PC-2 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/PLDs (Programmable Logic Device) | |
| Manufacturer | Intel/Altera | |
| Packaging | PDIP-40 | |
| Voltage - Supply(VCCIO) | 4.75V~5.25V | |
| Operating Temperature | 0℃~+70℃ | |
| Logic Array Blocks | - | |
| Type | EPLD |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
High-density logic device replacing TTL and 74HC. Functionally and pin-compatible with Altera EP910. High-speed, propagation delay tpd μ = 45 ns. All registers individually clocked asynchronously, or grouped register operation via two synchronous clocks. 24 macrocells with configurable I/O architecture, supporting 36 inputs and 24 outputs. "Zero-power" (typical standby current 20μA). Programmable registers offer D, T, SR, or JK flip-flops with independent asynchronous clear control. 100% universal testability — ensures 100% programming yield. Programmable security bit provides comprehensive protection for proprietary designs. Package options include 40-pin 600-mil DIP and 44-pin J-lead chip carrier. Full software support with schematic capture, netlist, Boolean equation, and state machine design entry methods.
Features
- High-density logic device replacement for TTL and 74HC
- Functionally and pin-compatible with Altera EP910
- High speed, propagation delay tpd μ = 45 ns
- All registers asynchronously clocked, or grouped register operation via two synchronous clocks
- 24 macrocells with configurable I/O architecture, supporting 36 inputs and 24 outputs
- "Zero-power" (typical standby current 20μA)
- Programmable registers provide D, T, SR, or JK flip-flops with independent asynchronous clear
- 100% universal testability — ensures 100% programming yield
- Programmable "security bit" for full protection of proprietary designs
- Package options: 40-pin 600-mil DIP and 44-pin J-lead chip carrier
- Full software support with schematic capture, netlist, Boolean equation, and state machine design entry methods
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/PLDs (Programmable Logic Device) | |
| Manufacturer | Intel/Altera | |
| Packaging | PDIP-40 | |
| Voltage - Supply(VCCIO) | 4.75V~5.25V | |
| Operating Temperature | 0℃~+70℃ | |
| Logic Array Blocks | - | |
| Type | EPLD |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
High-density logic device replacing TTL and 74HC. Functionally and pin-compatible with Altera EP910. High-speed, propagation delay tpd μ = 45 ns. All registers individually clocked asynchronously, or grouped register operation via two synchronous clocks. 24 macrocells with configurable I/O architecture, supporting 36 inputs and 24 outputs. "Zero-power" (typical standby current 20μA). Programmable registers offer D, T, SR, or JK flip-flops with independent asynchronous clear control. 100% universal testability — ensures 100% programming yield. Programmable security bit provides comprehensive protection for proprietary designs. Package options include 40-pin 600-mil DIP and 44-pin J-lead chip carrier. Full software support with schematic capture, netlist, Boolean equation, and state machine design entry methods.
Features
- High-density logic device replacement for TTL and 74HC
- Functionally and pin-compatible with Altera EP910
- High speed, propagation delay tpd μ = 45 ns
- All registers asynchronously clocked, or grouped register operation via two synchronous clocks
- 24 macrocells with configurable I/O architecture, supporting 36 inputs and 24 outputs
- "Zero-power" (typical standby current 20μA)
- Programmable registers provide D, T, SR, or JK flip-flops with independent asynchronous clear
- 100% universal testability — ensures 100% programming yield
- Programmable "security bit" for full protection of proprietary designs
- Package options: 40-pin 600-mil DIP and 44-pin J-lead chip carrier
- Full software support with schematic capture, netlist, Boolean equation, and state machine design entry methods
Compliance & Export Codes
| Type | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |