micron MT46V32M16CY-5B IT:J

Products Specifications

Type	Description	All
Category	Integrated Circuits (ICs)/Memory/Memory (ICs)
Manufacturer	micron
Packaging	FBGA-60
Refresh Current	5mA
Voltage - Supply	2.5V~2.7V
Memory Size	512Mbit
Operating temperature	-40℃~+85℃
Clock Frequency	200MHz
Features	Auto precharge function;Data mask function
Memory Format	DDR SDRAM
Current - Supply	75mA

AI Translation

VDD = 2.5V±0.2V, VDDQ = 2.5V±0.2V; VDD = 2.6V±0.1V, VDDQ = 2.6V±0.1V (DDR400)
Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two - one per byte)
Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-aligned with data for WHITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Data mask (DM) for masking write data (x16 has two - one per byte)
Programmable burst lengths: 2, 4, or 8
Auto refresh
- 64ms, 8192-cycle (AIT)
- 16ms, 8192-cycle (AAT)
Self refresh (not available on AAT devices)
Longer-lead TSOP for improved reliability (OCPL)
2.5V I/O (SSTL_2 compatible)
Concurrent auto precharge option is supported
tRAS lockout supported (tRAP = tRCD)
AEC-Q100
PPAP Submission
8D Response time

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Qty	Unit Price(Reference Only)	Total Amount
1+	$ 8.0003	$ 8.00
10+	$ 6.9109	$ 69.11
30+	$ 6.2471	$ 187.41
100+	$ 5.6915	$ 569.15
Standard Packaging2000/Full Reel

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Type	Description	All
Category	Integrated Circuits (ICs)/Memory/Memory (ICs)
Manufacturer	micron
Packaging	FBGA-60
Refresh Current	5mA
Voltage - Supply	2.5V~2.7V
Memory Size	512Mbit
Operating temperature	-40℃~+85℃
Clock Frequency	200MHz
Features	Auto precharge function;Data mask function
Memory Format	DDR SDRAM
Current - Supply	75mA

AI Translation

VDD = 2.5V±0.2V, VDDQ = 2.5V±0.2V; VDD = 2.6V±0.1V, VDDQ = 2.6V±0.1V (DDR400)
Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two - one per byte)
Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-aligned with data for WHITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Data mask (DM) for masking write data (x16 has two - one per byte)
Programmable burst lengths: 2, 4, or 8
Auto refresh
- 64ms, 8192-cycle (AIT)
- 16ms, 8192-cycle (AAT)
Self refresh (not available on AAT devices)
Longer-lead TSOP for improved reliability (OCPL)
2.5V I/O (SSTL_2 compatible)
Concurrent auto precharge option is supported
tRAS lockout supported (tRAP = tRCD)
AEC-Q100
PPAP Submission
8D Response time