Nanya Tech NT5AD512M16C4-HR

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks, 4 bank group with 4 banks for each bank group for x8 and eight-banks, 2 bank group with 4 banks for each bankgroup for x16 DRAM. The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR4 SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an ACTIVATE Command, which is then followed by a Read or Write command. The address bits registered coincident with the ACTIVATE Command are used to select the bank and row to be activated (BG0 - BG1 in x8 and BG0 in x16 select the bankgroup; BA0 - BA1 select the bank; A0 - A15 select the row; refer to Addressing section for more details. The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register. Prior to normal operation, the DDR4 SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation.

• Data Integrity
  • Auto Self Refresh (ASR) by DRAM built-in TS
  • Auto Refresh and Self Refresh Modes
• DRAM Access Bandwidth
  • Separated IO gating structures by Bank Groups
  • Self Refresh Abort
  • Fine Granularity Refresh
• Signal Synchronization
  • Write Leveling via MR settings1
  • Read Leveling via MPR
• Reliability & Error Handling
  • Command/Address Parity
  • Databus Write CRC
  • MPR readout
  • Boundary Scan (X16)
  • Post Package Repair
• Signal Integrity
  • Internal VREFDQ Training
  • Read Preamble Training
  • Gear Down Mode
  • Per DRAM Addressability
  • Configurable DS for system compatibility
  • Configurable On-Die Termination
  • Data bus inversion (DBI)
  • ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 Ω ± 1%)
• Power Saving & Efficiency
  • POD with VDDQ termination - Command/Address Latency (CAL) - Maximum Power Saving - Low-power Auto Self Refresh (LPASR)
• Programmable Functions
  • Output Driver Impedance (34/48)
  • CAS Write Latency (9/10/11/12/14/16/18/20)
  • Additive Latency (0/CL - 1/CL - 2)
  • CS to Command Address Latency (3/4/5/6/8)
  • Command Address Parity Latency (4/5/6)
  • Write Recovery Time (10/12/14/16/18/20/24)
  • Burst Type (Sequential/Interleaved)
  • RTT_PARK (34/40/48/60/80/120/240)
  • RTT_NOM (34/40/48/60/80/120/240)
  • RTT_WR (80/120/240)
  • Read Preamble (1T/2T)
  • Write Preamble (1T/2T)
  • Burst Length (BL8/BC4/BC4 or 8 on the fly)
  • LPASR (Manual: Normal/Reduced/Extended, Auto:TS)
• Options
  • Speed Grade (CL - TRCD - TRP) 2 - 2666 Mbps / 19 - 19 - 19 - 3200 Mbps / 22 - 22 - 22
  • Temperature Range (Tc) 5 - Commercial Grade : 0℃ ~ 95℃
  • VDD/VDDQ/VPP - 1.2V / 1.2V / 2.5V
  • Package information: Lead-free RoHS compliance and Halogen-free