- Pinout Diagram
- Footprint Diagram
Nexperia 74LVC2G04GW,125
| Manufacturer | |
| MPN | 74LVC2G04GW,125 |
| LCSC Part # | C192549 |
| Packaging | SOT-363 |
| Customer # | |
| Key Attributes | Dual inverter |
| Datasheet |  Nexperia 74LVC2G04GW,125 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | Nexperia | |
| Packaging | SOT-363 | |
| Logic Family | 74LVC | |
| Input Type | Schmitt trigger | |
| Voltage - Supply | 1.65V~5.5V | |
| Output Logic Level - Low | 800mV | |
| Propagation Delay | 3.2ns@5V,50pF | |
| Features | Power shutdown protection;Noise suppression function | |
| Operating Temperature | -40℃~+125℃ | |
| Input Logic Level - Low | 700mV;800mV | |
| Input Logic Level - High | 1.7V~2V | |
| Number of Circuits | 2 | |
| Output Logic Level - High | 2V | |
| Quiescent Current(Iq) | 4uA | |
| Number of Channels | 2 | |
| Current - Output High(IOH) | 32mA | |
| Current - Output Low(IOL) | 32mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC2G04 is a dual inverter. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power-down applications using IOFF. The l(OFF) circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Features
- Wide supply voltage range from 1.65 V to 5.5 V
- Overvoltage tolerant inputs to 5.5 V
- High noise immunity
- ±24 mA output drive (V(CC)=3.0 V)
- CMOS low power dissipation
- Direct interface with TTL levels
- IOFF circuitry provides partial Power-down mode operation
- Latch-up performance exceeds 250 mA
- Complies with JEDEC standard:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- JESD36 (4.6 V to 5.5 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Applications
- Level translation in mixed 3.3V and 5V environments
- Direct TTL-level interface
| Qty | Unit Price | Total Amount |
|---|---|---|
| 5+ | $ 0.1466$ 0.1452 | $ 0.73 |
| 50+ | $ 0.1153$ 0.1142 | $ 5.71 |
| 150+ | $ 0.0997$ 0.0987 | $ 14.81 |
| 500+ | $ 0.088$ 0.0872 | $ 43.60 |
| 3,000+ | $ 0.0754$ 0.0747 | $ 224.10 |
| 6,000+ | $ 0.0707$ 0.0700 | $ 420.00 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | Nexperia | |
| Packaging | SOT-363 | |
| Logic Family | 74LVC | |
| Input Type | Schmitt trigger | |
| Voltage - Supply | 1.65V~5.5V | |
| Output Logic Level - Low | 800mV | |
| Propagation Delay | 3.2ns@5V,50pF | |
| Features | Power shutdown protection;Noise suppression function | |
| Operating Temperature | -40℃~+125℃ | |
| Input Logic Level - Low | 700mV;800mV | |
| Input Logic Level - High | 1.7V~2V | |
| Number of Circuits | 2 | |
| Output Logic Level - High | 2V | |
| Quiescent Current(Iq) | 4uA | |
| Number of Channels | 2 | |
| Current - Output High(IOH) | 32mA | |
| Current - Output Low(IOL) | 32mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC2G04 is a dual inverter. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power-down applications using IOFF. The l(OFF) circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Features
- Wide supply voltage range from 1.65 V to 5.5 V
- Overvoltage tolerant inputs to 5.5 V
- High noise immunity
- ±24 mA output drive (V(CC)=3.0 V)
- CMOS low power dissipation
- Direct interface with TTL levels
- IOFF circuitry provides partial Power-down mode operation
- Latch-up performance exceeds 250 mA
- Complies with JEDEC standard:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- JESD36 (4.6 V to 5.5 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Applications
- Level translation in mixed 3.3V and 5V environments
- Direct TTL-level interface
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |