ADI AD9640ABCPZRL7-80
| Manufacturer | |
| MPN | AD9640ABCPZRL7-80 |
| LCSC Part # | C496481 |
| Packaging | LFCSP-64(9x9) |
| Customer # | |
| Key Attributes | 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Manufacturer | ADI | |
| Packaging | LFCSP-64(9x9) | |
| Operating Temperature | -40℃~+85℃ | |
| Interface | SPI | |
| Quiescent Current (Iq) | - | |
| Voltage - Supply | 1.7V~1.9V | |
| Number of Channels | 2 | |
| Integral non - linearity | 0.4LSB | |
| Voltage Reference | Built-in | |
| Clock/Oscillator | External | |
| Clock Frequency | 20MHz~80MHz | |
| Features | Input buffer;Synchronous triggering | |
| Resolution(Bits) | 80MHz;14 | |
| S/N Ratio | 72.1dB | |
| ADC architecture | - | |
| Programmable Gain | Not supported |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 750 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
AI Translation
The AD9640 is a dual 14-bit, 80/105/125/150 MSPS analog-to-digital converter (ADC). The AD9640 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth.
Features
AI Translation
- SNR = 71.8 dBc (72.8 dBFS) to 70 MHz @ 125 MSPS
- SFDR = 85 dBc to 70 MHz @ 125 MSPS
- Low power: 750 mW @ 125 MSPS
- SNR = 71.6 dBc (72.6 dBFS) to 70 MHz @ 150 MSPS
- SFDR = 84 dBc to 70 MHz @ 150 MSPS
- Low power: 820 mW @ 150 MSPS
- 1.8 V analog supply operation
- 1.8 V to 3.3V CMOS output supply or 1.8 V LVDS output supply
- Integer 1 to 8 input clock divider
- IF sampling frequencies to 450 MHz
- Internal ADC voltage reference
- Integrated ADC sample-and-hold inputs
- Flexible analog input range: 1 V p-p to 2 V p-p
- Differential analog inputs with 650 MHz bandwidth
- ADC clock duty cycle stabilizer
- 95 dB channel isolation/crosstalk
- Serial port control
- User-configurable, built-in self-test (BIST) capability
- Energy-saving power-down modes
- Integrated receive features Fast detect/threshold bits Composite signal monitor
Applications
AI Translation
- Communications
- Diversity radio systems
- Multimode digital receivers
- GSM, EDGE, WCDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems
- Smart antenna systems
- General-purpose software radios
- Broadband data applications
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 174.4091 | $ 174.41 |
| 10+ | $ 159.4592 | $ 1594.59 |
Standard Packaging750/Full Reel | ||
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Manufacturer | ADI | |
| Packaging | LFCSP-64(9x9) | |
| Operating Temperature | -40℃~+85℃ | |
| Interface | SPI | |
| Quiescent Current (Iq) | - | |
| Voltage - Supply | 1.7V~1.9V | |
| Number of Channels | 2 | |
| Integral non - linearity | 0.4LSB | |
| Voltage Reference | Built-in | |
| Clock/Oscillator | External | |
| Clock Frequency | 20MHz~80MHz | |
| Features | Input buffer;Synchronous triggering | |
| Resolution(Bits) | 80MHz;14 | |
| S/N Ratio | 72.1dB | |
| ADC architecture | - | |
| Programmable Gain | Not supported |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 750 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
AI Translation
The AD9640 is a dual 14-bit, 80/105/125/150 MSPS analog-to-digital converter (ADC). The AD9640 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth.
Features
AI Translation
- SNR = 71.8 dBc (72.8 dBFS) to 70 MHz @ 125 MSPS
- SFDR = 85 dBc to 70 MHz @ 125 MSPS
- Low power: 750 mW @ 125 MSPS
- SNR = 71.6 dBc (72.6 dBFS) to 70 MHz @ 150 MSPS
- SFDR = 84 dBc to 70 MHz @ 150 MSPS
- Low power: 820 mW @ 150 MSPS
- 1.8 V analog supply operation
- 1.8 V to 3.3V CMOS output supply or 1.8 V LVDS output supply
- Integer 1 to 8 input clock divider
- IF sampling frequencies to 450 MHz
- Internal ADC voltage reference
- Integrated ADC sample-and-hold inputs
- Flexible analog input range: 1 V p-p to 2 V p-p
- Differential analog inputs with 650 MHz bandwidth
- ADC clock duty cycle stabilizer
- 95 dB channel isolation/crosstalk
- Serial port control
- User-configurable, built-in self-test (BIST) capability
- Energy-saving power-down modes
- Integrated receive features Fast detect/threshold bits Composite signal monitor
Applications
AI Translation
- Communications
- Diversity radio systems
- Multimode digital receivers
- GSM, EDGE, WCDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems
- Smart antenna systems
- General-purpose software radios
- Broadband data applications
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991C3 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991C3 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



