Infineon SAF-XC161CJ-16F40F BB
| Manufacturer | |
| MPN | SAF-XC161CJ-16F40F BB |
| LCSC Part # | C538666 |
| Packaging | TQFP-144(20x20) |
| Customer # | |
| Key Attributes | 16-Bit Single-Chip Microcontroller with C166SV2 Core |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon | |
| Packaging | TQFP-144(20x20) |
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Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- High Performance 16-bit CPU with 5-Stage Pipeline
- 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
- 1-Cycle Multiplication (16x16 bit), Background Division (32 / 16 bit) in 21 Cycles
- 1-Cycle Multiply-and-Accumulate (MAC) Instructions
- Enhanced Boolean Bit Manipulation Facilities
- Zero-Cycle Jump Execution
- Additional Instructions to Support HLL and Operating Systems
- Register-Based Design with Multiple Variable Register Banks
- Fast Context Switching Support with Two Additional Local Register Banks
- 16 Mbytes Total Linear Address Space for Code and Data
- 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
- 16-Priority-Level Interrupt System with 73 Sources, Sample-Rate down to 50 ns
- 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
- Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or via Prescaler (factors 1:1 … 60:1)
- On-Chip Memory Modules: 2 Kbytes On-Chip Dual-Port RAM (DPRAM), 4 Kbytes On-Chip Data SRAM (DSRAM), 2 Kbytes On-Chip Program/Data SRAM (PSRAM), 128 Kbytes On-Chip Program Memory (Flash Memory)
- On-Chip Peripheral Modules: 12-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and Conversion Time (down to 2.55 μs or 2.15 μs), Two 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins), Multi-Functional General Purpose Timer Unit with 5 Timers, Two Synchronous/Asynchronous Serial Channels (USARTs), Two High-Speed-Synchronous Serial Channels, On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects (Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality, Serial Data Link Module (SDLM), compliant with J1850, supporting Class 2, IIC Bus Interface (10-bit addressing, 400 kbit/s) with 3 Channels (multiplexed), On-Chip Real Time Clock, Driven by Dedicated Oscillator
- Idle, Sleep, and Power Down Modes with Flexible Power Management
- Programmable Watchdog Timer and Oscillator Watchdog
- Up to 12 Mbytes External Address Space for Code and Data
- Programmable External Bus Characteristics for Different Address Ranges: Multiplexed or Demultiplexed External Address/Data Buses, Selectable Address Bus Width, 16-Bit or 8-Bit Data Bus Width, Five Programmable Chip-Select Signals, Hold- and Hold-Acknowledge Bus Arbitration Support
- Up to 99 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
- On-Chip Bootstrap Loader Supported by a Large Range of Developm
In-Stock: 3
3 In stock, ships now
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| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 43.7993 | $ 43.80 |
| 10+ | $ 42.3842 | $ 423.84 |
Standard Packaging1000/Full Tray | ||
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Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |



