IC Plus IP101GR

IP101G is an IEEE 802.3/802.3u compliant single-port Fast Ethernet Transceiver for both 100Mbps and 10Mbps operations. It supports Auto MDI/MDIX function to simplify the network installation and reduce the system maintenance cost. To improve the system performance, IP101G provides a hardware interrupt pin to indicate the link, speed and duplex status change. IP101G provides Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) to connect with different types of 10/100Mbps Media Access Controller (MAC). IP101G is designed to use category 5 unshielded twisted-pair cable or Fiber-Optic cables connecting to other LAN devices. A PECL interface is supported to connect with an external 100Base-FX fiber optical transceiver. Except good performance, reliability, rich power saving method and extreme low operating current, IP101G provides a serial tool for system designers to complete their projects easily. They are System Debug Assistant Tool and EMI Management Tool. IP101G is fabricated with advanced CMOS (85nm) technology and design is based on IC Plus’s 5th Ethernet-PHY architecture, this feature makes IP101G consumes very low power. Such as in the full load operation (100Mbps_FDX), it only takes below 0.15W. IP101GA / IP101GR&IP101GRI are available in 48LQFP/32QFN, lead-free package.

• 10/100Mbps IEEE 802.3/802.3u compliant
• Fast Ethernet transceiver
• Supports 100Base-TX/FX Media Interface
• Supports MII/ RMII Interface
• Supports Auto MDI/MDIX function
• Power Management Tool APS, auto power saving while Link-off 802.3az, protocol based power saving WOL+, light traffic power saving PWD, force-off power saving
• Supports MII with LPI for RX and TX
• Supports RMII with LPI for RX
• Supports Base Line Wander compensation
• Supports Interrupt function
• Built in synchronization FIFO to support jumbo frame size up to 12KB in MII mode (10KB in RMII 100Mbps mode)
• Supports MDC and MDIO to communicate with the MAC
• EMI Management Tool F/W based control 4 levels for mapping the difference layout length on the PCB
• Single 3.3V power supply
• Built-in Vcore regulator
• DSP-based PHY Transceiver technology
• System Debug Assistant Tool 16 bit RX counter 9 bit RXError/CRC counter
• Isolate MII/RMII RX to TX Loopback
• Loopback MII/RMII Using either 25MHz crystal/oscillator or 50MHz oscillator REF_CLK as clock source
• Built-in 49.9ohm resistors for simplifying BOM
• Flexible LED display
• Process: 85nm

-NAS-Network printers and Servers-IP Set-Top BOX-IP/Smart TV-game console IP and Video Phone-PoE telecom Fiber Device