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SAMSUNG K4A4G165WE-BCRC product image
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SAMSUNG K4A4G165WE-BCRCRoHS

Manufacturer
SAMSUNG
MPN
K4A4G165WE-BCRC
LCSC Part #
C2803250
Packaging
FBGA-96
Customer #
Key Attributes
DDR4 SDRAM
Datasheetpdf iconSAMSUNG K4A4G165WE-BCRC
In-Stock: 22
22 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 14.7885$ 14.79
10+$ 13.9704$ 139.70
30+$ 12.5523$ 376.57
112+$ 10.3533$ 1159.57
Standard Packaging112/Full Tray
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory (ICs)
ManufacturerSAMSUNG
PackagingFBGA-96
Refresh Current13mA
Memory Size4Gbit
Voltage - Supply1.14V~1.26V
Operating temperature0℃~+95℃
Clock Frequency1.2GHz
FeaturesAuto precharge function;Asynchronous reset function;CRC function;ZQ calibration function;Dynamic on-chip termination;Data mask function
Memory FormatDDR4 SDRAM
Current - Supply35mA
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging112
Sales UnitPiece

Features

AI Translation
  • JEDEC standard 1.2V (1.14V~1.26V)
  • VDDQ = 1.2V (1.14V~1.26V)
  • VPP = 2.5V (2.375V~2.75V)
  • 800 MHz fCK for 1600Mb/sec/pin, 933 MHz fCK for 1866Mb/sec/pin, 1067MHz fCK for 2133Mb/sec/pin, 1200MHz fCK for 2400Mb/sec/pin
  • 8 Banks (2 Bank Groups)
  • Programmable CAS Latency(posted CAS): 10, 11, 12, 13, 14, 15, 16, 17, 18
  • Programmable CAS Write Latency (CWL) = 9, 11 (DDR4-1600), 10, 12 (DDR4-1866), 11, 14 (DDR4-2133) and 12, 16 (DDR4-2400)
  • 8-bit pre-fetch
  • Burst Length: 8, 4 with ICCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]
  • Bi-directional Differential Data-Strobe
  • Internal(self) calibration: Internal self calibration through ZQ pin (RZQ: 240 ohm ±1%)
  • On Die Termination using ODT pin
  • Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C
  • Asynchronous Reset
  • Package: 96 balls FBGA - x16
  • All of Lead-Free products are compliant for RoHS
  • All of products are Halogen-free
  • CRC(Cyclic Redundancy Check) for Read/Write data security
  • Command address parity check
  • DBI(Data Bus Inversion)
  • Gear down mode POD (Pseudo Open Drain) interface for data input/output
  • Internal VREF for data inputs
  • External VPP for DRAM Activating Power
  • PPR is supported