TI SN74LVC1T45DCKR

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VccA. VccA accepts any supply voltage from 1.65V to 5.5V. The B port is designed to track VccB. VccB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. The SN74LVC1T45 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The SN74LVC1T45 is designed so that the DIR input circuit is supplied by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

• Available in the Texas Instruments NanoStar and NanoFree Packages
• Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
• Vcc Isolation Feature - If Either Vcc Input Is at GND, Both Ports Are in the High-Impedance State
• DIR Input Circuit Referenced to VccA
• Low Power Consumption, 4-μA Max Icc
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode Operation
• Max Data Rates:
  • 420 Mbps (3.3-V to 5-V Translation)
  • 210 Mbps (Translate to 3.3 V)
  • 140 Mbps (Translate to 2.5 V)
  • 75 Mbps (Translate to 1.8 V)
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22:
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)