- Pinout Diagram
- Footprint Diagram
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EDA ModelsEasyEDA
STC Micro STC90C52RC-40I-LQFP44
| Manufacturer | STC MicroAsian Brands |
| MPN | STC90C52RC-40I-LQFP44 |
| LCSC Part # | C91838 |
| Packaging | LQFP-44(10x10) |
| Customer # | |
| Key Attributes | 51 Family 8 Bit 40MHz 39 LQFP-44(10x10) Microcontrollers RoHS |
| Datasheet |  STC Micro STC90C52RC-40I-LQFP44 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | STC Micro | |
| Packaging | LQFP-44(10x10) | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 3.5V~5.5V | |
| Program Storage Size | 8KB | |
| CPU Core | 51 Family | |
| Core Size | 8 Bit | |
| CPU Maximum Speed | 40MHz | |
| Oscillator Type | Built-in+External | |
| Number of I/O | 39 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 160 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- High-speed: 1 clock/machine cycle, enhanced 8051 core, 7–12× faster than classic 8051, also 20% faster than STC's early 1T series MCUs (e.g., STC12/11/10 series)
- Wide voltage range: 2.4V–5.5V
- Low-power design: slow-speed mode, idle mode, power-down mode (wake-up via external interrupt or internal power-down wake-up timer)
- No external reset required; 16 selectable reset threshold voltages during ISP programming; built-in high-reliability reset circuit
- No external crystal required; internal clock selectable from 5MHz–35MHz (equivalent to standard 8051: 60–420MHz); internal high-precision R/C oscillator (±0.3%); ±1% temperature drift (−40°C–+85°C); ±0.6% temperature drift at room temperature (−20°C–+65°C)
- Power-down wake-up sources: INT0/INT1 (rising/falling edge); INT2/INT3/INT4 (falling edge); CCP0/CCP1/CCP2/RxD/T0/T2 pins; dedicated internal power-down wake-up timer
- 4K/8K/13K/15.5K bytes on-chip Flash program memory; endurance >100,000 erase/write cycles
- Large-capacity on-chip EEPROM; endurance >100,000 erase/write cycles
- ISP/IAP in-system/in-application programmable; no programmer or emulator required
- High-speed ADC: 8-channel, 10-bit, up to 300,000 samples/sec; 3-channel PWM also usable as 3-channel DAC
- Comparator: supports comparison between external pin CMP+ and external pin CMP−, generates interrupt, outputs on pin CMPO (configurable polarity); also supports comparison between CMP+ and internal reference voltage
- 3-channel capture/compare unit (CCP/PCA/PWM) — also configurable as 3-channel DAC, 3 timers, or 3 external interrupts (rising/falling edge)
- 5 timers: two 16-bit auto-reload timer/counters (T0/T2; T0 compatible with standard 8051 timer/counter), both support programmable clock output; 3-channel CCP/PCA provides 3 additional timers
- Programmable clock output (divides internal system clock or external clock input): T0 outputs clock on P3.5; T2 outputs clock on P3.0; all 3 timer/counter clock outputs support 1–65536 division; internal master clock output on P5.4/MCLKO (STC15 series 8-pin MCUs output master clock on P3.4/MCLKO)
- Hardware watchdog timer (WDT)
- Ultra-high-speed UART; time-division multiplexing supports 3 independent serial ports
- SPI high-speed synchronous serial interface
- Advanced instruction set architecture, compatible with standard 8051 instruction set; hardware multiply/divide instructions
- General-purpose I/O (26/18/14 pins); quasi-bidirectional/weak pull-up after reset (standard 8051 I/O mode); 4 configurable modes: quasi-bidirectional/weak pull-up, push-pull/strong pull-up, input-only/high-impedance, open-drain; each I/O pin sink/source capability up to 20mA; total chip current not to exceed 120mA
- No external crystal required; integrated high-precision R/C oscillator (±0.3%); ±1% temperature drift (−40°C–+85°C); ±0.6% temperature drift at room temperature (−20°C–+65°C)
- No external reset required; integrated high-reliability reset circuit; 16 selectable reset threshold voltages during ISP programming; external reset circuit also supported
- Unbreakable encryption; Macro Crystal 9th-generation encryption technology
- Exceptional noise immunity: high ESD protection, passes 20kV ESD system-level test; passes 4kV EFT test; wide voltage range tolerates power supply fluctuations; wide temperature range −40°C–+85°C
- Significant EMI reduction: configurable internal clock, 1 clock/machine cycle, supports low-frequency clock operation
- Ultra-low power consumption: power-down mode <0.1μA (external interrupt wake-up); idle mode typical <1mA; normal operating mode 4mA–6mA; power-down mode wake-up via external interrupt or dedicated internal timer; suitable for battery-powered systems
- In-system emulation and in-system programming; no dedicated programmer or emulator required; supports remote firmware upgrade
Not available now
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | STC Micro | |
| Packaging | LQFP-44(10x10) | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 3.5V~5.5V | |
| Program Storage Size | 8KB | |
| CPU Core | 51 Family | |
| Core Size | 8 Bit | |
| CPU Maximum Speed | 40MHz | |
| Oscillator Type | Built-in+External | |
| Number of I/O | 39 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 160 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- High-speed: 1 clock/machine cycle, enhanced 8051 core, 7–12× faster than classic 8051, also 20% faster than STC's early 1T series MCUs (e.g., STC12/11/10 series)
- Wide voltage range: 2.4V–5.5V
- Low-power design: slow-speed mode, idle mode, power-down mode (wake-up via external interrupt or internal power-down wake-up timer)
- No external reset required; 16 selectable reset threshold voltages during ISP programming; built-in high-reliability reset circuit
- No external crystal required; internal clock selectable from 5MHz–35MHz (equivalent to standard 8051: 60–420MHz); internal high-precision R/C oscillator (±0.3%); ±1% temperature drift (−40°C–+85°C); ±0.6% temperature drift at room temperature (−20°C–+65°C)
- Power-down wake-up sources: INT0/INT1 (rising/falling edge); INT2/INT3/INT4 (falling edge); CCP0/CCP1/CCP2/RxD/T0/T2 pins; dedicated internal power-down wake-up timer
- 4K/8K/13K/15.5K bytes on-chip Flash program memory; endurance >100,000 erase/write cycles
- Large-capacity on-chip EEPROM; endurance >100,000 erase/write cycles
- ISP/IAP in-system/in-application programmable; no programmer or emulator required
- High-speed ADC: 8-channel, 10-bit, up to 300,000 samples/sec; 3-channel PWM also usable as 3-channel DAC
- Comparator: supports comparison between external pin CMP+ and external pin CMP−, generates interrupt, outputs on pin CMPO (configurable polarity); also supports comparison between CMP+ and internal reference voltage
- 3-channel capture/compare unit (CCP/PCA/PWM) — also configurable as 3-channel DAC, 3 timers, or 3 external interrupts (rising/falling edge)
- 5 timers: two 16-bit auto-reload timer/counters (T0/T2; T0 compatible with standard 8051 timer/counter), both support programmable clock output; 3-channel CCP/PCA provides 3 additional timers
- Programmable clock output (divides internal system clock or external clock input): T0 outputs clock on P3.5; T2 outputs clock on P3.0; all 3 timer/counter clock outputs support 1–65536 division; internal master clock output on P5.4/MCLKO (STC15 series 8-pin MCUs output master clock on P3.4/MCLKO)
- Hardware watchdog timer (WDT)
- Ultra-high-speed UART; time-division multiplexing supports 3 independent serial ports
- SPI high-speed synchronous serial interface
- Advanced instruction set architecture, compatible with standard 8051 instruction set; hardware multiply/divide instructions
- General-purpose I/O (26/18/14 pins); quasi-bidirectional/weak pull-up after reset (standard 8051 I/O mode); 4 configurable modes: quasi-bidirectional/weak pull-up, push-pull/strong pull-up, input-only/high-impedance, open-drain; each I/O pin sink/source capability up to 20mA; total chip current not to exceed 120mA
- No external crystal required; integrated high-precision R/C oscillator (±0.3%); ±1% temperature drift (−40°C–+85°C); ±0.6% temperature drift at room temperature (−20°C–+65°C)
- No external reset required; integrated high-reliability reset circuit; 16 selectable reset threshold voltages during ISP programming; external reset circuit also supported
- Unbreakable encryption; Macro Crystal 9th-generation encryption technology
- Exceptional noise immunity: high ESD protection, passes 20kV ESD system-level test; passes 4kV EFT test; wide voltage range tolerates power supply fluctuations; wide temperature range −40°C–+85°C
- Significant EMI reduction: configurable internal clock, 1 clock/machine cycle, supports low-frequency clock operation
- Ultra-low power consumption: power-down mode <0.1μA (external interrupt wake-up); idle mode typical <1mA; normal operating mode 4mA–6mA; power-down mode wake-up via external interrupt or dedicated internal timer; suitable for battery-powered systems
- In-system emulation and in-system programming; no dedicated programmer or emulator required; supports remote firmware upgrade
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |