onsemi MC74HC390ADTR2G

The MC74HC390A is identical in pinout to the LS390. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two independent 4−bit counters, each composed of a divide−by−two and a divide−by−five section. The divide−by−two and divide−by−five counters have separate clock inputs, and can be cascaded to implement various combinations of ÷2 and/or ÷5 up to a÷100 counter. Flip−flops internal to the counters are triggered by high−to−low transitions of the clock input. A separate, asynchronous reset is provided for each 4−bit counter. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or strobes except when gated with the Clock of the HC390A.

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 μA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No 7 A
• Chip Complexity: 244 FETs or 61 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

• Each half of the MC54/74HC390A has independent ÷2 and ÷5 sections (except for the Reset function). The ÷2 and ÷5 counters can be connected to give BCD or bi−quinary (2−5) count sequences.
• If Output QA is connected to the Clock B input, a decade divider with BCD output is obtained.
• To obtain a bi−quinary count sequence, the input signals connected to the Clock B input, and output QD is connected to the Clock A input. QA provides a 50% duty cycle output.