onsemi MC14526BDWR2G

The MC14526B binary counter is constructed with MOS P−channel and N−channel enhancement mode devices in a monolithic structure. This device is presettable, cascadable, synchronous down counter with a decoded state output for divide−by−N applications. In single stage applications the "0" output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide−by−N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock. This complementary MOS counter can be used in frequency synthesizers, phase−locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge−Clocked Design: Incremented on Positive Transition of Clock or Negative Transition of Inhibit
• Asynchronous Preset Enable
• Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range
• This Device is Pb−Free and is RoHS Compliant

• frequency synthesizers
• phase−locked loops
• other frequency division applications requiring low power dissipation and/or high noise immunity