ST M24C32-WMN6TP

The M24C32, M24C64 and M24128 devices are |²C -compatible electrically erasable programmable memories (EEPROM). They are organized as 4096x8 bits, 8192x8 bits and 16384x8 bits, respectively. |²C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the |²C bus definition. The device behaves as a slave in the |²C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (R̅W̅) (as described in Table 3), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an

• Two-wire |²C serial interface supports 400 kHz protocol
• Single supply voltages: 2.5 V to 5.5 V, 1.8 V to 5.5 V, 1.7 V to 5.5 V
• Write Control input
• Byte and Page Write
• Random and Sequential Read modes
• Self-timed programming cycle
• Automatic address incrementing
• Enhanced ESD/latch-up protection
• More than 1 Million write cycles
• More than 40-year data retention
• Packages – ECOPACK (RoHS compliant)