TI SN74LVC138ADR

The SN54LVC138A 3- line to 8- line decoder/demultiplexer is designed for 2.7- V to 3.6 - V VCC operation, and the SN74LVC138A 3- line to 8- line decoder/demultiplexer is designed for 1.65- V to 3.6 - V VCC operation. The 'LVC138A devices are designed for high- performance memory- decoding or data- routing applications requiring very short propagation delay times. In high- performance memory systems, these decoders minimize the effects of system decoding. When employed with high- speed memories utilizing a fast enable circuit, delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary- select inputs and the three enable inputs select one of eight output lines. Two active- low enable inputs and one active- high enable input reduce the need for external gates or inverters when expanding. A 24- line decoder can be implemented without external inverters, and a 32- line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. Inputs can be driven from either 3.3- V or 5- V devices. This feature allows the use of these devices as translatr in a mixed 3.3- V/5- V system environment.

• Operate From 1.65 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max tpd of 5.8 ns at 3.3 V
• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25℃
• Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25℃
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)