TI SN74LVC125APWR

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

• Operates From 1.65 V to 3.6 V
• Specified From -40℃ to 85℃ and -40℃ to 125℃
• Inputs Accept Voltages to 5.5 V
• Max tpd of 4.8 ns at 3.3 V
• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25℃
• Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25℃
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)