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TI SN74LVC16374ADGGRRoHS

Manufacturer
TI
MPN
SN74LVC16374ADGGR
LCSC Part #
C7665
Packaging
TSSOP-48-6.1mm
Customer #
Key Attributes
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Datasheetpdf iconTI SN74LVC16374ADGGR
In-Stock: 44
44 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 1.4886$ 1.49
10+$ 1.2324$ 12.32
30+$ 1.0913$ 32.74
100+$ 0.9308$ 93.08
500+$ 0.8611$ 430.55
1,000+$ 0.8286$ 828.60
Standard Packaging2000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Flip Flops
ManufacturerTI
PackagingTSSOP-48-6.1mm
Operating Temperature-40℃~+85℃
Voltage - Supply1.65V~3.6V
Number of Bits per Element8
Series74LVC Series
Output TypeTri-State
Number of Elements2
Current - Output High(IOH)24mA
Current - Output Low(IOL)24mA
Setup Time1.9ns
Quiescent Current20uA
Hold Time1.9ns
Propagation Delay4.5ns@3.3V,50pF
Trigger TypeRising Edge
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2000
Sales UnitPiece

Introduction

AI Translation

This 16-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC16374A is particularly suitable for implementing buffer registers, 1/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Features

AI Translation
  • Member of the Texas Instruments Widebus Family
  • Typical v(oLP) (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25℃
  • Typical v(oHV) (Output v(oH) Undershoot) > 2V at VCC = 3.3V, TA = 25℃
  • Ioff Supports Partial-Power-Down Mode Operation
  • Supports Mixed-Mode Signal Operation on All Ports (5-V Input and Output Voltages With 3.3-V VCC)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)