Nexperia HEF4541BT,118
| Manufacturer | |
| MPN | HEF4541BT,118 |
| LCSC Part # | C7508475 |
| Packaging | SC-70 |
| Customer # | |
| Key Attributes | SC-70 Programmable Timers and Oscillators RoHS |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Programmable Timers and Oscillators | |
| Manufacturer | Nexperia | |
| Packaging | SC-70 |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The HEF4541B is a programmable timer. It consists of a 16-stage binary counter, an integrated oscillator to be used with external timing components, an automatic power-on reset and output control logic. The external components RTC and CTC determines the frequency of the oscillator within the frequency range ↑Hz to 100 kHz. An external clock signal at input RS can replace the oscillator. The timer advances on the positive-going transition of RS. A LOW on the auto reset input (AR) and a LOW on the master reset input (MR) enables the internal power-on reset. A HIGH level at input MR resets the counter independent on all other inputs. Resetting, disables the oscillator to provide no active power dissipation. A HIGH at input AR turns off the power-on reset to provide a low quiescent power dissipation of the timer. The 16-stage counter divides the oscillator frequency by 2^8, 2^10, 2^13 or 2^16 depending on the state of the address inputs (A0, A1). The divided oscillator frequency is available at output O. The phase input (PH) features a complementary output signal. When the mode select input (MODE) is LOW the timer is a single transition timer and when HIGH the timer is a 2^n frequency divider. It operates over a recommended VDD power supply range of 2 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.
Features
- Wide supply voltage range from 3.0 V to 15.0 V
- CMOS low power dissipation
- High noise immunity
- Fully static operation
- 5 V, 10 V, and 15 V parametric ratings
- Standardized symmetrical output characteristics
- Complies with JEDEC standard JESD 13-B
- ESD protection: HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- Specified from -40 ℃ to +85 ℃ and from -40 ℃ to +125 ℃
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.873 | $ 0.87 |
| 10+ | $ 0.7075 | $ 7.08 |
| 30+ | $ 0.6248 | $ 18.74 |
| 100+ | $ 0.542 | $ 54.20 |
| 500+ | $ 0.4933 | $ 246.65 |
| 1,000+ | $ 0.469 | $ 469.00 |
Standard Packaging2500/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Programmable Timers and Oscillators | |
| Manufacturer | Nexperia | |
| Packaging | SC-70 |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The HEF4541B is a programmable timer. It consists of a 16-stage binary counter, an integrated oscillator to be used with external timing components, an automatic power-on reset and output control logic. The external components RTC and CTC determines the frequency of the oscillator within the frequency range ↑Hz to 100 kHz. An external clock signal at input RS can replace the oscillator. The timer advances on the positive-going transition of RS. A LOW on the auto reset input (AR) and a LOW on the master reset input (MR) enables the internal power-on reset. A HIGH level at input MR resets the counter independent on all other inputs. Resetting, disables the oscillator to provide no active power dissipation. A HIGH at input AR turns off the power-on reset to provide a low quiescent power dissipation of the timer. The 16-stage counter divides the oscillator frequency by 2^8, 2^10, 2^13 or 2^16 depending on the state of the address inputs (A0, A1). The divided oscillator frequency is available at output O. The phase input (PH) features a complementary output signal. When the mode select input (MODE) is LOW the timer is a single transition timer and when HIGH the timer is a 2^n frequency divider. It operates over a recommended VDD power supply range of 2 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.
Features
- Wide supply voltage range from 3.0 V to 15.0 V
- CMOS low power dissipation
- High noise immunity
- Fully static operation
- 5 V, 10 V, and 15 V parametric ratings
- Standardized symmetrical output characteristics
- Complies with JEDEC standard JESD 13-B
- ESD protection: HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- Specified from -40 ℃ to +85 ℃ and from -40 ℃ to +125 ℃
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8541100000 |
| USHTS | 8541100040 |
| TARIC | 8541100000 |
| CAHTS | 8541100090 |
| BRHTS | 85411011 |
| INHTS | 85411000 |
| MXHTS | 8541.10.01 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8541100000 |
| USHTS | 8541100040 |
| TARIC | 8541100000 |
| Type | Details |
|---|---|
| CAHTS | 8541100090 |
| BRHTS | 85411011 |
| INHTS | 85411000 |
| MXHTS | 8541.10.01 |



