RENESAS 9DB433AGLFT

The 9DB433 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB433 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator.

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment
• OE# pins; suitable for Express Card applications
• PLL or bypass mode; PLL can dejitter incoming clock
• Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs
• Spread spectrum compatible; tracks spreading input clock for low EMI
• SMBus interface; unused outputs can be disabled
• Supports undriven differential outputs in Power Down mode for power management
• 4 0.7V current-mode differential HCSL output pairs
• Supports zero delay buffer mode and fanout mode
• Selectable bandwidth
• 50–110MHz operation in PLL mode
• 5–166MHz operation in Bypass mode

• 4 output PCIe Gen1–3 zero-delay/fanout buffer