TI CD4044BPWR
| Manufacturer | |
| MPN | CD4044BPWR |
| LCSC Part # | C74801 |
| Packaging | TSSOP-16 |
| Customer # | |
| Key Attributes | CMOS Quad 3-State R/S Latches |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Latches | |
| Manufacturer | TI | |
| Packaging | TSSOP-16 | |
| Quiescent Current | 1uA | |
| Series | 4000B | |
| Logic Type | - | |
| Voltage - Supply | 3V~18V | |
| Current - Output Low(IOL) | 6.8mA | |
| Operating Temperature | -55℃~+125℃ | |
| Output Type | Tri-State | |
| Setup Time | - | |
| Number of Channels | 4 | |
| Current - Output High(IOH) | 6.8mA | |
| Hold Time | - | |
| Propagation Delay | 50ns |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
CD4043B types are quad crosscoupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch.states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The ppen circuit feature allows common busing of the outputs.
Features
- 3-state outputs with common output ENABLE
- Separate SET and RESET inputs for each latch
- NOR and NAND configurations
- 5-V, 10-V, and 15-V parametric ratings
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 20V
- Maximum input current of μA at 78V over full package temperature range; 100 nA at 18 V and 25℃
- Noise margin (over full package temperature range): 1 V at VDD = 5V; 2V at VDD = 10V; 2.5V at VDD = 15V
- Meets all requirements of JEDEC Tentative Standard No. 1aB, *Standard Specifications for Description of B' Series CMOS Devices"
- Holding register in multi-register system
- Four bits of independent storage with output ENABLE
- Strobed register
- General digital logic
- CD4643B for positive logic systems
- CD4044B for negative logic systems
Applications
- Holding register in multi-register system
- Strobed register
- General digital logic
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.2723 | $ 0.27 |
| 10+ | $ 0.2658 | $ 2.66 |
| 30+ | $ 0.2625 | $ 7.88 |
| 100+ | $ 0.2593 | $ 25.93 |
Standard Packaging2000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Latches | |
| Manufacturer | TI | |
| Packaging | TSSOP-16 | |
| Quiescent Current | 1uA | |
| Series | 4000B | |
| Logic Type | - | |
| Voltage - Supply | 3V~18V | |
| Current - Output Low(IOL) | 6.8mA | |
| Operating Temperature | -55℃~+125℃ | |
| Output Type | Tri-State | |
| Setup Time | - | |
| Number of Channels | 4 | |
| Current - Output High(IOH) | 6.8mA | |
| Hold Time | - | |
| Propagation Delay | 50ns |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
CD4043B types are quad crosscoupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch.states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The ppen circuit feature allows common busing of the outputs.
Features
- 3-state outputs with common output ENABLE
- Separate SET and RESET inputs for each latch
- NOR and NAND configurations
- 5-V, 10-V, and 15-V parametric ratings
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 20V
- Maximum input current of μA at 78V over full package temperature range; 100 nA at 18 V and 25℃
- Noise margin (over full package temperature range): 1 V at VDD = 5V; 2V at VDD = 10V; 2.5V at VDD = 15V
- Meets all requirements of JEDEC Tentative Standard No. 1aB, *Standard Specifications for Description of B' Series CMOS Devices"
- Holding register in multi-register system
- Four bits of independent storage with output ENABLE
- Strobed register
- General digital logic
- CD4643B for positive logic systems
- CD4044B for negative logic systems
Applications
- Holding register in multi-register system
- Strobed register
- General digital logic
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



