RENESAS UPD48288236AFF-E24-DW1-E2

The μPD48288209A is a 33,554,432-word by 9 bit, the μPD48288218A is a 16,777,216-word by 18 bit and the μPD48288236A is a 8,388,608-word by 36 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell. The μPD48288209A, μPD48288218A and μPD48288236A integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (CK and CK#) are latched on the positive edge of CK and CK#. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration.

• SRAM-type interface
• Double-data-rate architecture
• PLL circuitry
• Cycle time: 1.875 ns @ trc = 15 ns
• 2.5 ns @ trc = 15 ns
• 2.5 ns @ tRC = 20 ns
• 3.3 ns @ tRC = 20 ns
• Non-multiplexed addresses
• Multiplexing option is available.
• Data mask for WRITE commands
• Differential input clocks (CK and CK#)
• Differential input data clocks (DK and DK#)
• Data valid signal (QVLD)
• Programmable burst length: 2|4|8 (x9 / x18 / x36)
• User programmable impedance output (25 Ω - 60 Ω)
• JTAG boundary scan