NXP SJA1105QELY

The SJA1105P/Q/R/S safe and secure automotive gigabit Ethernet switch family extends the capabilities of the SJA1105/SJA1105T [1] switches with improved security-related features, extended interface options, and ISO 26262 ASIL-A compliance. The SJA1105P/Q/R/S is a 5-port automotive Ethernet switch supporting IEEE Audio Video Bridging (AVB) and Time-Sensitive Networking (TSN) standards. Each of the five ports can be individually configured to operate at 10/100/1000 Mbit/s. This feature provides the flexibility to connect any Fast/Gigabit/optical PHY or MCU/MPU to any of the ports. Examples of external PHYs are the TJA1100 and TJA1102 IEEE 100BASE-T1 PHYs from NXP Semiconductors ([2] and [3]). The new frame white/blacklisting, port-reachability and address learning restriction features, available on all SJA1105P/Q/R/S variants, improve switch security by limiting data processing to known frames and data sources and preventing the forwarding of erroneous or malicious data. The updated MII/RMII/RGMII interfaces offer extended IO voltages such as 1V8 and 3V3 RGMII. Furthermore, the SGMII interface available on the /R and /S variants extends the connectivity options of the switch. The /P and /Q variants do not feature an SGMII port and remain 100 % pin-compatible with the SJA1105/SJA1105T switches. The SJA1105P/Q/R/S switch family was developed according to the ISO 26262 standard. ASIL-A compliance reduces the safety-critical ECU design load. Additional documentation, including a safety manual, is available on request. The switches are compatible with the IEEE AVB standard. The /Q and /S variants support extended TSN features such as 802.1Qbv. NXP-original AUTOSAR drivers and AVB SW stack are available for this series.

• 5-port store and forward architecture
• Each port individually configurable for 10/100 Mbit/s when operated as MII/RMII and 10/100/1000 Mbit/s when operated as RGMII or SGMII
• Independent I/O voltage domains: selectable 1.8/2.5/3.3 V operation for MII/RMII/ RGMII; selectable 1.8/2.5/3.3 V for host interfacing; 1.2 V core voltage domains
• Small footprint: LFBGA159 (12 mm × 12 mm) package
• Automotive Grade 2 ambient operating temperature: -40 °C to +105 °C
• Automotive product qualification in accordance with AEC-Q100 Rev-H
• ISO-26262, ASIL-A
• IEEE 802.3 compliant
• 128 kB frame buffer
• 1024 entry TCAM for collision-free MAC address learning
• 2 kB frame length handling
• IEEE 802.1Q defined tag support
• 4096 VLANs supported
• Egress tagging/untagging on a per-VLAN basis per port
• Priority-based QoS handling as specified in IEEE 802.1Q
• Per-port priority remapping and 8 configurable egress queues per port
• Optional double-tagging support
• Hardware support for IEEE 802.1AS timestamping and IEEE 802.1Qav AVB traffic shaping
• 16 credit-based shapers available according to IEEE 802.1Qav; shapers can be freely allocated to any priority queue on a per port basis
• Support for SR Class A, Class B, and Class C traffic
• IEEE 1588v2 one-step sync forwarding in hardware
• Frame mirroring and retagging for enhanced diagnostics
• Statistics for dropped frames and buffer load
• RFC2819 support for counters
• IEEE 802.1X hardware support for EAP filtering, reachability and disabling address learning
• Extensive filtering rules for frame forwarding - Retagging/ Tunneling/ Double Tagging
• Address learning space can be configured for static and learned addresses
• Enhanced support for address learning restrictions for security
• Ingress rate-limiting on a per-port basis for Unicast/Multicast and Broadcast traffic
• Broadcast storm protection
• IEEE 802.1Qbv time-aware traffic (SJA1105/Q/S only)
• IEEE 802.1Qci per-stream policing (pre-standard) (SJA1105/Q/S only)
• Support for ring-based redundancy (for time-triggered traffic only) (SJA1105/Q/S only)
• 1024 deterministic Ethernet flows with per-flow based: – Time-triggered traffic transmission – Ingress policing and reception window check – Statistics (SJA1105/Q/S only)
• MII/RMII for interfacing with 10/100 Mbit/s PHYs/host processor (Fast Ethernet)
• RGMII for interfacing with 10/100/1000 Mbit/s PHYs/host processor/cascading (Gigabit Ethernet); internal delay for interface connection without external delay components
• SGMII for interfacing with 10/100/1000 Mbit/s PHYs/host processor/cascading
• MAC and PHY modes for interfacing (MII/RMII/RGMII/SGMII) directly with another switch or host processor
• Programmable drive strength for MII/RMII/RGMII interfaces
• SPI for host processor access
• 25 MHz system clock input from crystal oscillator or AC-coupled single-ended clock
• 25 MHz reference clock output
• Device reset input from host processor
• Synchronization output for cascading devices
• IEEE 1149.1/1149.6 compliant JTAG interface for TAP controller access and BSCAN