LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
Cart
TI SN74LVC1G74RSER product image
  • SN74LVC1G74RSER thumbnail 1
  • SN74LVC1G74RSER thumbnail 2
  • SN74LVC1G74RSER thumbnail 3
  • Pinout
  • Footprint
Images for reference only

TI SN74LVC1G74RSERRoHS

Manufacturer
TI
MPN
SN74LVC1G74RSER
LCSC Part #
C717743
Packaging
UQFN-8(1.5x1.5)
Customer #
Key Attributes
1.65V~5.5V 1 1 4.4ns@5V,50pF UQFN-8(1.5x1.5) Flip Flops RoHS
Datasheetpdf iconTI SN74LVC1G74RSER
In-Stock: 90
90 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 0.3584$ 0.36
10+$ 0.3503$ 3.50
30+$ 0.3454$ 10.36
100+$ 0.3389$ 33.89
Standard Packaging5000/Full Reel
Better price for more quantity?
$

Products Specifications

Show similar products (0) >
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Flip Flops
ManufacturerTI
PackagingUQFN-8(1.5x1.5)
Operating Temperature-40℃~+85℃
Voltage - Supply1.65V~5.5V
Number of Bits per Element1
Series74LVC Series
Output TypeComplementary type
Number of Elements1
Current - Output High(IOH)32mA
Current - Output Low(IOL)32mA
Quiescent Current10uA
Propagation Delay4.4ns@5V,50pF
Trigger TypeRising Edge
Report an ErrorShow similar products (0) >

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging5000
Sales UnitPiece

Introduction

AI Translation

This single-bit, positive-edge-triggered D-type flip-flop operates from 1.65V to 5.5V VCC. NanoFree™ packaging technology represents a significant breakthrough in IC packaging concepts, using the silicon die itself as the package. A low level on the preset (PRE) or clear (CLR) input sets or resets the output regardless of the levels of other inputs. When PRE and CLR are inactive (high), data at the D input that meets the setup time requirement is transferred to the output on the positive edge of the clock pulse. Clock triggering occurs at a specific voltage level and is not directly related to the rise time of the clock pulse. After the hold time interval, the data at the D input can be changed without affecting the output level. This device fully meets the specifications for partial power-down applications using Ioff. The Ioff circuit disables the outputs, preventing destructive backflow current from the device when it is powered down.

Features

AI Translation
  • NanoFree™ package
  • 5V VCC operation
  • Inputs accept up to 5.5V
  • Down translation to VCC
  • tpd max 5.9ns at 3.3V
  • Low power, ICC max 10μA
  • ±24mA output drive at 3.3V
  • VOLP (output ground bounce) typ < 0.8V (VCC = 3.3V, TA = 25℃)
  • VOHV (output VOH undershoot) typ > 2V (VCC = 3.3V, TA = 25℃)
  • Ioff supports hot insertion, partial power-down mode, and back-drive protection
  • Latch-up performance exceeds 100mA per JESD 78 Class II
  • ESD protection exceeds JESD 22
    • 2000V Human Body Model
    • 200V Machine Model
    • 1000V Charged Device Model

Applications

AI Translation
  • Servers
  • LED displays
  • Network switches
  • Telecom infrastructure
  • Motor drivers
  • I/O expanders