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FMD(Fremont Micro Devices) FT61F145-TRB product image
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FMD(Fremont Micro Devices) FT61F145-TRBRoHS

Manufacturer
MPN
FT61F145-TRB
LCSC Part #
C708797
Packaging
TSSOP-20
Customer #
Key Attributes
High-performance RISC CPU microcontroller
Datasheetpdf iconFMD(Fremont Micro Devices) FT61F145-TRB
In-Stock: 372
372 In stock, ships now
Not recommended for new designs
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QtyUnit PriceTotal Amount
1+$ 0.4089$ 0.41
10+$ 0.3365$ 3.37
48+$ 0.3048$ 14.63
96+$ 0.2671$ 25.64
480+$ 0.249$ 119.52
1,008+$ 0.2384$ 240.31
Standard Packaging48/Full Tube

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microcontrollers
ManufacturerFMD(Fremont Micro Devices)
PackagingTSSOP-20
ADC (Bit)12bit
Voltage - Supply1.9V~5.5V
Program Memory TypeFLASH
Program Storage Size4KB
CPU CoreOthers
CPU Maximum Speed16MHz
Number of I/O18

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging48
Sales UnitPiece

Features

AI Translation
  • 49 instructions, all single-cycle except branch/jump instructions
  • Memory architecture: Program ROM 4k × 14bits, Data RAM 512 × 8bits, Data EEPROM 128 × 8bits, program code sector protection (1 sector = 1k × 14bits), IAP supported, VDD ≥ 2.7V
  • 16-level hardware stack
  • Selectable instruction cycle: 2T/4T
  • System clock: 8MHz (VDD ≥ 1.9V), 16MHz (VDD ≥ 2.7V)
  • Operating temperature range: -40°C to 85°C
  • Wide operating voltage range: 1.9V − 5.5V
  • Clock sources: Two internal clocks — 16M high-speed high-accuracy HIRC (software trimming supported, 2.5% per step), 32K low-speed low-power LIRC; crystal oscillator and external clock input; crystal clock missing detection; dual-speed clock startup in crystal clock configuration; slow clock cycle measurement
  • 16-bit watchdog with 7-bit prescaler, selectable clock source
  • Power-on reset delay counter
  • Low-power SLEEP mode, system clock optionally kept running or disabled
  • LVR: 2.0V / 2.2V / 2.5V / 2.8V / 3.1V / 3.6V / 4.1V
  • LVD: Internal voltage 2.0V / 2.4V / 2.8V / 3.0V / 3.6V / 4.0V, or external input voltage
  • ISP and OCD supported: 3 hardware breakpoints, soft reset, single-step, pause, step-over, etc.
  • Program ROM sector protection
  • Package options: SOP8, MSOP10, SOP14, SOP16, SOP20, QFN20, TSSOP20
  • GPIO: 18 general-purpose IOs with independent direction control (PORTA, PORTB, PORTC); 18 wake-up pins (edge or level detection); 18 pins with individual pull-up control; 18 pins with individual pull-down control; external reset pin PC0; 18 programmable source current (4(8)/26mA@5V, PC0 and PC1 support 4/8/26mA@5V); 18 programmable sink current (max. 62mA@5V); pin alternate function remapping supported
  • Communication interface: 1 × USART
  • 1 × 12-bit SAR ADC: 7 external channels + 1 × ¼VDD channel; ADC input channels AN0–AN6; internal reference voltage VDD, 0.5V, 2V, 3V; external reference VREFP, VREFN; manual and auto trigger modes; delayed trigger supported
  • TIM1 – 16-bit: 16-bit timer with 16-bit prescaler; auto-reload; clock sources: system clock, HIRC, multiplied clock (2× crystal or HIRC), LIRC; double-buffered period and duty cycle registers; 4 independent capture/compare/PWM channels; PWM supports edge-aligned, center-aligned, and one-pulse modes; 3 complementary PWM output pairs with dead-time control; leading-edge blanking; fault brake control
  • TIM2 – 16-bit: 16-bit timer with 15-bit prescaler; auto-reload; clock sources: system clock, HIRC, multiplied clock (2× crystal or HIRC), LIRC; double-buffered period and duty cycle registers; 3 independent capture/compare/PWM channels
  • TIM4 – 8-bit: Basic timer with 8-bit prescaler, selectable clock source