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FMD(Fremont Micro Devices) FT61F143-RB product image
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FMD(Fremont Micro Devices) FT61F143-RBRoHS

Manufacturer
FMD(Fremont Micro Devices)Asian Brands
MPN
FT61F143-RB
LCSC Part #
C708795
Packaging
SOP-16
Customer #
Key Attributes
High-performance RISC CPU microcontroller
Datasheetpdf iconFMD(Fremont Micro Devices) FT61F143-RB
In-Stock: 820
820 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
5+$ 0.4756$ 2.38
50+$ 0.3661$ 18.31
150+$ 0.3191$ 47.87
500+$ 0.2597$ 129.85
2,500+$ 0.2347$ 586.75
5,000+$ 0.2175$ 1087.50
Standard Packaging50/Full Tube
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microcontrollers
ManufacturerFMD(Fremont Micro Devices)
PackagingSOP-16
ADC (Bit)12bit
Voltage - Supply1.9V~5.5V
Program Memory TypeFLASH
Program Storage Size4KB
CPU CoreOthers
CPU Maximum Speed16MHz
Number of I/O14
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Additional Information

TypeDetails
Minimum5
Multiple5
Standard Packaging50
Sales UnitPiece

Features

AI Translation
  • 49 instructions, all single-cycle except branch/jump instructions
  • Memory architecture: Program ROM 4k x 14bits, Data RAM 512 x 8bits, Data EEPROM 128 x 8bits, program code sector protection, 1 sector ≈ 1k x 14bits, IAP supported
  • 16-level hardware stack
  • Selectable instruction cycle: 2T/4T, minimum instruction cycle 125ns at 16MHz@2T (VDD≥1.9V)
  • Operating temperature range: -40°C - 85°C
  • Wide operating voltage range: 1.9V − 5.5V
  • Clock sources: two internal clocks (16M high-speed high-accuracy HIRC with software trimming, 2.5‰ per step; 32K low-speed low-power LIRC), crystal oscillator and external clock input, crystal clock missing detection, dual-speed clock startup slow clock cycle measurement in crystal clock configuration
  • 16-bit watchdog with 7-bit prescaler, selectable clock source
  • Power-on reset delay counter
  • Low-power SLEEP mode, system clock selectable to remain active or shut down
  • LVR: 2.0V/2.2V/2.5V/2.8V/3.1V/3.6V/4.1V
  • LVD: internal voltage 2.0V/2.4V/2.8V/3.0V/3.6V/4.0V, or external input voltage
  • ISP and on-chip debugging OCD supported, 3 hardware breakpoints, soft reset, single step, halt, step over, etc.
  • Program ROM sector protection
  • Package options: SOP8, MSOP10, SOP14, SOP16, SOP20, QFN20, TSSOP20
  • 18 individually direction-controlled general-purpose IOs: PORTA, PORTB, PORTC
  • 18 wake-up pins: edge or level detection
  • 18 pins with individually controlled pull-up
  • 18 pins with individually controlled pull-down
  • External reset pin: PC0
  • 18 programmable source current pins: 4/26mA@5V; PC0 and PC1 support 4/8/26mA@5V
  • 18 programmable sink current IOs: max. 62mA@5V
  • Pin alternate function remapping supported
  • 1 x USART
  • 1 x 12-bit SAR ADC, 7 external channels + 1 x 1/4VDD channel, ADC input channels: AN0~AN6, internal reference voltage: VDD, 0.5V, 2V, 3V, external reference: VREFP, VREFN, manual and auto trigger modes, delayed trigger supported
  • TIM1 - 16bit: 16-bit timer with 16-bit prescaler, auto-reload, clock sources: system clock, HIRC, multiplied clock (2x crystal or HIRC), LIRC, double-buffered period and duty cycle registers, 4 independent capture/compare/PWM channels, PWM supports edge-aligned, center-aligned, and one-pulse modes, 3 pairs of complementary PWM outputs with dead-time control, leading-edge blanking, fault brake control
  • TIM2 - 16bit: 16-bit timer with 15-bit prescaler, auto-reload, clock sources: system clock, HIRC, multiplied clock (2x crystal or HIRC), LIRC, double-buffered period and duty cycle registers, 3 independent capture/compare/PWM channels
  • TIM4 - 8bit: basic timer with 8-bit prescaler, selectable clock source