RENESAS 72V36100L7-5BB

72V36100/72V36110 are ultra-deep, high-speed CMOS FIFO memories with clocked read/write operation and flexible x36/x18/x9 bus-matching data flow. These FIFOs offer users several key advantages:

• Flexible x36/x18/x9 bus-matching on both read and write ports.
• Fixed and short retransmit operation cycle count.
• Fixed and short first-word latency — the delay from writing the first data word into an empty FIFO to when it can be read.
• Asynchronous/synchronous conversion support on read and write ports.
• High-density storage up to 4 Mbit.

Bus-matching synchronous FIFOs are ideally suited for networking, video, telecommunications, data communications, and other applications requiring large data buffering with mismatched bus widths.

Each FIFO has a data input port (Dn) and a data output port (Qn), whose widths can be configured to 36-bit, 18-bit, or 9-bit during the master reset cycle based on the states of the external control pins: Input Width (IW), Output Width (OW), and Bus Match (BM).

The input port can be configured as either a synchronous (clocked) or asynchronous interface. In synchronous operation, the input port is controlled by the Write Clock (WCLK) input and Write Enable (WEN) input. When WEN (active low) is asserted, data on the Dn input is written into the FIFO on each rising edge of WCLK. In asynchronous operation, only the WR input is used to write data into the FIFO. Data is written on the rising edge of WR, and the WEN (active low) input should be tied to its active state (low).

The output port can be configured as either a synchronous (clocked) or asynchronous interface. In synchronous operation, the output port is controlled by the Read Clock (RCLK) input and Read Enable (REN) input. When REN (active low) is asserted, data is read from the FIFO on each rising edge of RCLK. In asynchronous operation, only the RD input is used to read data from the FIFO. Data is read on the rising edge of RD, and the REN (active low) input should be tied to its active state (low). When the output port is configured for asynchronous operation, the FIFO must be configured in standard mode, and the OE input is used to three-state the Qn outputs.

The frequencies of RCLK and WCLK can vary fully independently between 0 and fMAX. There is no restriction on the frequency of one clock input relative to the other.

These devices support two possible operating timing modes: Standard mode and First Word Fall Through (FWFT) mode.

In standard mode, the first word written into an empty FIFO does not appear on the data output lines until a specific read operation is performed. The read operation consists of asserting REN (active low) and applying a rising edge to RCLK, which transfers the word from internal memory to the data output lines.

In FWFT mode, the first word written into an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN (active low) does not need to be asserted to access the first word. However, subsequent words written to the FIFO require REN (active low) to be low for access. The state of the FWFT/SI input during master reset determines which timing mode is used. For applications requiring more data storage capacity than a single FIFO can provide, FWFT timing mode enables depth expansion by cascading FIFOs in series (i.e., the data output of one FIFO connected to the corresponding input of the next).

• Choose among the following memory organizations: 72V36100 65,536 x 36 72V36110 131,072 x 36
• Higher density, 2Meg and 4Meg SuperSync II FIFOs
• Up to 166 MHz Operation of the Clocks
• User selectable Asynchronous read and/or write ports (PBGA & CABGA Only)
• User selectable input and output port bus-sizing
  • x36 in to x36 out
  • x36 in to x18 out
  • x36 in to x9 out
  • x18 in to x36 out
  • x9 in to x36 out
• Big-Endian/Little-Endian user selectable byte representation
• 5V input tolerant
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select Standard timing (using EF and FF flags) or First Word Fall Through timing (using 0.8 (overline) and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• JTAG port, provided for Boundary Scan function (PBGA & CABGA Only)
• Independent Read and Write Clocks (permit reading and writing simultaneously)
• Available in a 128-pin Thin Quad Flat Pack (TQFP) or a 144-pin Plastic Ball Grid Array (PBGA) (with additional features), or a 144-pin Chip Array BGA (CABGA) (with additional features)
• Pin compatible to the SuperSync II (72V3640/72V3650/72V3660/ 72V3670/72V3680/72V3690) family
• High-performance submicron CMOS technology
• Industrial temperature range ( -40℃ to +85℃) is available
• Green parts available, see ordering information

Network, Video, Telecom, Datacom