TI TMS32C6203BGNZA250

The TMS320C6203B device is part of the TMS320C62xTM fixed-point DSP generation in the TMS320C6000TM DSP platform. The C62xTM DSP devices are based on the high-performance, advanced VelociTITM very-long-instruction-word (VLiW) architecture, making these DSPs an excellent choice for multichannel and multifunction applications. The TMS320C62xTM DSP offers cost-effective solutions to high-performance DSP-programming challenges. The TMS320C6203B has a performance capability of up to 2400 MIPS at a clock rate of 300 MHz. The C6203B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result.

• 4-, 3.33-ns Instruction Cycle Time
• 250-, 300-MHz Clock Rate
• Eight 32-Bit Instructions/Cycle
• 2000, 2400 MIPS
• C6203B and C6202 GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 GLW BGA Package
• C6203B and C6202B GNZ, GNY and ZNY Packages are Pin-Compatible
• VelociTITM Advanced Very-Long-Instruction Word (VLIW) C62xTM DSP Core
• Eight Highly Independent Functional Units: Six ALUs (32-/40-Bit), Two 16-Bit Multipliers (32-Bit Result)
• Load-Store Architecture With 32 32-Bit General-Purpose Registers
• Instruction Packing Reduces Code Size
• All Instructions Conditional
• Instruction Set Features: Byte-Addressable (8-, 16-, 32-Bit Data), 8-Bit Overflow Protection, Saturation, Bit-Field Extract, Set, Clear, Bit-Counting, Normalization
• 7M-Bit On-Chip SRAM: 3M-Bit Internal Program/Cache (96K 32-Bit Instructions), 4M-Bit Dual-Access Internal Data (512K Bytes), Organized as Two 256K-Byte Blocks for Improved Concurrency
• 32-Bit External Memory Interface (EMIF): Glueless Interface to Synchronous Memories (SDRAM or SBSRAM), Glueless Interface to Asynchronous Memories (SRAM and EPROM), 52M-Byte Addressable External Memory Space
• Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
• Flexible Phase-Locked-Loop (PLL) Clock Generator
• 32-Bit Expansion Bus (XBus): Glueless/Low-Glue Interface to Popular PCI Bridge Chips, Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses, Master/Slave Functionality, Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals
• Three Multichannel Buffered Serial Ports (McBSPs): Direct Interface to T1/E1, MVIP, SCSA Framers, ST-Bus-Switching Compatible, Up to 256 Channels Each, AC97-Compatible
• Serial-Peripheral Interface (SPI) Compatible (MotorolaTM)
• Two 32-Bit General-Purpose Timers
• IEEE-1149.1 (JTAG#) Boundary-Scan-Compatible
• 352-Pin BGA Package (GNZ)
• 384-Pin BGA Package (GLS)
• 384-Pin BGA Packages (GNY and ZNY)
• 0.15-μm/5-Level Metal Process - CMos Technology
• 3.3-V I/Os, 1.5-V Internal

• Multi-channel and multi-function applications
• Three multichannel buffered serial ports (McBSPs)
• Two 32-bit general-purpose timers
• 32-bit expansion bus (XBus) supporting synchronous or asynchronous industry-standard host bus protocols
• 32-bit external memory interface (EMIF) compatible with SDRAM or SBSRAM and asynchronous peripheral interfaces