TI TMS320DM8168CCYGA2

The DM816x DaVinci™ Video Processor is a highly integrated, programmable platform that leverages TI's DaVinci™ technology to meet the processing requirements of the following applications: video encoding, decoding, transcoding and rate conversion, video security, video conferencing, video infrastructure, media servers, and digital signage. With the great flexibility offered by the fully integrated hybrid processor solution, this device enables OEM and ODM manufacturers to quickly bring devices with robust operating system support, rich user interfaces, and high processing performance to market. This device combines programmable video and audio processing with a highly integrated set of peripherals. The key to this device lies in up to three High-Definition Video and Imaging Coprocessors (HDVICP2). Each coprocessor can perform a single 1080p60 H.264 encoding or decoding, or multiple encodings and decodings at lower resolutions or frame rates. Additionally, multi-channel HD-to-HD or HD-to-SD code conversion and multiple encodings can also be accomplished. With the ability to simultaneously process 1080p60 data streams, the TMS320DM816x device is a powerful solution suitable for today's demanding HD video application requirements. Programmability is provided by an ARM® Cortex™-A8 RISC CPU with NEON™ extensions, a TI C674x VLIW floating-point DSP core, and high-definition video and imaging coprocessors. The ARM® allows developers to separate control functions from audio and video algorithms programmed on the DSP and coprocessors, thereby reducing the complexity of system software. The ARM® Cortex™-A8 32-bit RISC processor with NEON™ floating-point extensions includes: 32 kilobytes (KB) instruction cache; 32KB data cache; 256KB L2 cache; 48KB common ROM and 64

• High-performance DaVinci™ video processor
• ARM® Cortex™-A8 RISC processor up to 1.35GHz
• C674x Very Long Instruction Word (VLIW) DSP up to 1.125GHz
• Up to 9000 MIPS and 6750 MFLOPS
• In-order, dual-issue, superscalar architecture processor core
• NEON™ multimedia architecture with integer and floating-point support (VFPv3-IEEE754 compliant)
• Jazelle® Runtime Compiler Target (RCT) execution environment
• 32K-byte instruction and data cache
• 256K-byte L2 cache
• 64K-byte RAM, 48K-byte boot ROM
• 64 general-purpose registers (32-bit)
• Six ALU (32-bit and 40-bit) functional units
• 2 SP x SP → DP per 2 clocks
• 2 SP x DP → DP per 3 clocks
• 2 DP x DP → DP per 4 clocks
• Fixed-point multiply supports two 32 x 32-bit multiplications, four 16 x 16-bit multiplications (including complex multiply), or eight 8 x 8-bit multiplications
• C674x two-level memory architecture
• 32K-byte L1 program (L1P) and L1 data (L1D) RAM and cache
• 256K-byte L2 unified mapped RAM and cache
• System Memory Management Unit (system MMU)
• Maps C674x DSP and EDMA Task Control Block (TCB) memory accesses to system addresses
• 512K-byte On-Chip Memory Controller (OCMC) RAM
• Media controller
• Manages HDVPSS and HDVICP2 modules
• Up to three programmable HD Video Image Coprocessing (HDVICP2) engines
• Encode, decode, and transcode operations
• H.264, MPEG2, VC1, MPEG4 SP and ASP
• SGX530 3D graphics engine (available on DM8168 and DM8166 devices only)
• Up to 30 MTriangles per second
• Universal scalable rendering engine
• Direct3D® Mobile, OpenGL® ES 1.1 and 2.0, OpenVG™ 1.1, OpenMax™ API support
• Advanced geometry DMA-driven operations
• Programmable HQ image anti-aliasing
• Endianness
• ARM, DSP instruction and data
• Little-endian
• HD Video Processing Subsystem (HDVPSS)
• Two 165MHz HD video capture channels
• Each channel can be split into dual 8-bit capture channels
• Two 165MHz HD video display channels
• One 16-bit, 24-bit, 30-bit channel and one 16-bit channel
• Simultaneous SD and HD analog output
• HDMI 1.3 transmitter with PHY (HDCP with pixel clock up to 165MHz)
• Three graphics layers
• Dual 32-bit DDR2 and DDR3 SDRAM interfaces
• Supports up to DDR2-800 and DDR3-1600 memory
• Up to eight x8 devices total
• 2GB total address space
• Dynamic Memory Manager (DMM)
• Programmable multi-region memory mapping and interleaving
• Efficient 2D block access
• Tiled objects and mirroring at 0°, 90°, 180°, or 270° orientation
• Optimized interleaved access
• One PCI Express® (PCIe®) 2.0 port with integrated PHY
• Single port with one or two 5.0GT/s lanes
• Configurable as root complex or endpoint
• Serial ATA (SATA) 3.0Gbps controller with integrated PHY
• Direct interface to up to two hard disk drives
• Hardware-assisted Native Command Queuing (NCQ) from up to 32 entries
• Port multiplier and command-based switching support
• Two 10Mbps, 100Mbps, and 1000Mbps Ethernet MAC (EMAC)
• IEEE 802.3 compliant (3.3V IO only)
• MII and GMII media-independent interfaces
• Management Data I/O (MDIO) module
• Dual USB 2.0 ports with integrated PHY
• USB 2.0 high-speed and full-speed client
• USB 2.0 high-speed, full-speed, and low-speed host
• Endpoints 0–15 supported
• General-Purpose Memory Controller (GPMC)
• 8-bit and 16-bit multiplexed address and data bus
• Up to six chip selects (up to 256M-byte address space per chip select pin)
• Seamless interface to NOR flash, NAND flash (with BCH and Hamming ECC), SRAM, and pseudo-SRAM
• Error Location Module (ELM) external to GPMC provides up to 16-bit per 512-byte hardware ECC for NAND
• Flexible asynchronous protocol control for interfaces to FPGA, CPLD, ASIC, etc.
• Enhanced Direct Memory Access (EDMA) controller
• Four transfer controllers
• 64 independent DMA channels and 8 QDMA channels
• Seven 32-bit general-purpose timers
• One system watchdog timer
• Three configurable UART, IrDA, and CIR modules
• UART0 with modem control signals
• UART support up to 3.6864Mbps
• SIR, MIR, FIR (4.0 MBAUD), and CIR
• One 40MHz SPI with four chip selects
• SD and SDIO serial interfaces (1-bit and 4-bit)
• Dual I2C bus® ports
• Three multi-channel audio serial ports
• One six-serializer transmit and receive port
• Two dual-serializer transmit and receive ports
• DIT mode for S/PDIF and AES/EBU (all ports)
• Multi-channel Buffered Serial Port (McBSP)
• Transmit and receive clock up to 48MHz
• Two clock zones and two serial data pins
• TDM, I2S, and similar format support
• Real-Time Clock (RTC)
• One-shot or periodic interrupt generation
• Up to 64 GPIO pins
• On-chip ARM® ROM Boot Loader (RBL)
• Power, reset, and clock management
• SmartReflex™ technology (Class 2)
• Seven independent core power domains
• Clock enable and disable control for subsystems and peripherals
• IEEE 1149.1 (JTAG) and IEEE 1149.7 (cJTAG) compatible
• 1031-pin lead-free BGA package (CYG suffix), 0.65mm ball pitch
• Via Channel™ technology enables 0.8mm design rules
• 40nm CMOS process technology
• 3.3V single-ended LVCMOS I/O (except DDR3 at 1.5V, DDR2 at 1.8V, DEV_CLKIN at 1.8V)

• Video encoding, decoding, transcoding, and rate conversion
• Video security
• Video conferencing
• Video infrastructure
• Media servers
• Digital signage