TI TMS320DM6437ZWTQ6

The TMS320C64x+ DSPs (including the TMS320DM6437 device) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The DM6437 device is based on the third-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture, making these DSPs an excellent choice for digital media applications. The C64x+ devices are upward code-compatible from previous devices that are part of the C6000 DSP platform. The C64x DSPs support added functionality and have an expanded instruction set from previous devices.

With performance of up to 5600 million instructions per second (MIPS) at a clock rate of 700 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2800 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5600 MMACS.

• High-Performance Digital Media Processor
• 2.5-, 2.-, 1.67-, 1.51-, 1.43-ns Instruction Cycle Time
• 400-, 500-, 600, 660-, 700-MHz C64x+ Clock Rate
• Eight 32-Bit c64x+ Instructions/Cycle
• 3200, 4000, 4800, 5280, 5600 MIPS
• Fully Software-Compatible With c64x
• Commercial and Automotive (Q or S suffix) Grades
• Low-Power Device (L suffix)
• c64x+ Instruction Set Features:
  • Byte-Addressable (8-/16-/32-/64-Bit Data)
  • 8-Bit Overflow Protection
  • Bit-Field Extract, Set, Clear
  • Normalization, Saturation, Bit-Counting
  • VelociTI.2 Increased Orthogonality
  • c64x+ Extensions
  • Compact 16-bit Instructions
  • Additional Instructions to Support Complex Multiplies
• 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
• 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
• 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
• Supports Little Endian Mode Only
• Video Processing Subsystem (VPSS)
  • Front End Provides:
    • CCD and CMOS Imager Interface
    • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
    • Preview Engine for Real-Time Image Processing
    • Glueless Interface to Common Video Decoders
    • Histogram Module
    • Auto-Exposure, Auto-White Balance and Auto-Focus Module
    • Resize Engine
      • Resize Images From 1/4x to 4x
      • Separate Horizontal/Vertical Control
  • Back End Provides:
    • Hardware On-Screen Display (OSD)
    • Four 54-MHz DACs for a Combination of
      • Composite NTSC/PAL Video
      • Luma/Chroma Separate Video (S-video)
      • Component (YPbPr or RGB) Video (Progressive)
    • Digital Output
      • 8-/16-bit YUV or up to 24-Bit RGB
      • HD Resolution
      • Up to 2 Video Windows
• External Memory Interfaces (EMIFs)
  • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
  • Supports up to 333-MHz (data rate) Bus and Interfaces With DDR2-400 SDRAM
  • Asynchronous 8-Bit Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
  • Flash Memory Interfaces
    • NOR (8-Bit-Wide Data)
    • NAND (8-Bit-Wide Data)
• Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
• Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
• One 64-Bit Watch Dog Timer
• Two UARTs (One with RTS and CTS Flow Control)
• Master/Slave Inter-Integrated Circuit (I2C Bus)
• Two Multichannel Buffered Serial Ports (McBSPs)
  • I2S and TDM AC97 Audio Codec Interface
  • SPI Standard Voice Codec Interface (AIC12)
  • Telecom Interfaces
    • ST-Bus, H-100
  • 128 Channel Mode Multichannel Audio Serial Port (McASP0)
    • Four Serializers and SPDIF (DIT) Mode
• 16-Bit Host-Port Interface (HPI)
• High-End CAN Controller (HECC)
• 32-Bit 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface
• 10/100 Mb/s Ethernet MAC (EMAC)
  • IEEE 802.3 Compliant
  • Supports Media Independent Interface (MII)
  • Management Data I/O (MDIO) Module
• VLYNQ Interface (FPGA Interface)
• Three Pulse Width Modulator (PWM) Outputs
• On-Chip ROM Bootloader
• Individual Power-Savings Modes
• Flexible PLL Clock Generators
• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
• Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
• Packages:
  • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
  • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
• 0.09-μm/6-Level Cu Metal Process (CMOS)
• 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-L/-Q6/-Q5/-Q4)
• 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)

• Digital Media
• Networked Media
• Encode/Decode
• Video
• Imaging