ADI AD9649BCPZ-20

The AD9649 is a single-chip, single-channel, 14-bit, 20/40/65/80 MSPS ADC that operates from a 1.8 V supply and incorporates a high-performance sample-and-hold circuit and an on-chip voltage reference. The product features a multistage differential pipelined architecture with built-in output error correction logic, delivering 14-bit accuracy at 80 MSPS data rates with guaranteed no missing codes over the entire operating temperature range. The ADC incorporates multiple functional features to optimize device flexibility and minimize system cost, including programmable clock and data alignment and programmable digital test pattern generation. Available digital test patterns include built-in fixed and pseudorandom patterns, as well as user-defined test patterns input via the SPI. All internal conversion cycles are controlled by a differential clock input with a selectable divide ratio of 1, 2, or 4. Digital output data formats include offset binary, Gray code, or twos complement. A data output clock (DCO) is provided to ensure correct latching timing for the receiving logic. Both 1.8 V and 3.3 V CMOS logic levels are supported. The AD9649 is available in a 32-lead LFCSP package, is RoHS compliant, and is rated over the −40°C to +85°C industrial temperature range.

• 1.8 V analog supply
• 1.8 V to 3.3 V output supply
• SNR 74.3 dBFS (9.7 MHz input) 71.5 dBFS (200 MHz input)
• SFDR 93 dBc (9.7 MHz input) 80 dBc (200 MHz input)
• Low power 45 mW (20 MSPS) 87 mW (80 MSPS)
• Differential input, 700 MHz bandwidth
• On-chip voltage reference and sample-and-hold circuit
• 2 V P-P differential analog input
• DNL: ±0.35 LSB
• Serial port control options data format: offset binary, Gray code, or two's complement
• 1, 2, or 4 integer input clock divider
• Built-in optional digital test pattern generation
• Power-saving shutdown mode
• DCO with programmable clock and data alignment
• AD9649 operates from a single 1.8 V analog supply, with a separate supply for the digital output drivers to accommodate 1.8 V to 3.3 V logic levels
• Patented sample-and-hold circuit maintains excellent performance at input frequencies up to 200 MHz, with low cost, low power consumption, and ease of use
• Standard SPI supports various product features and functions, including: data output formatting, internal clock divider, power-down mode, DCO and data output (D13 to D0) timing and offset adjustment, and voltage reference mode
• AD9649 is available in a 32-lead LFCSP package, RoHS compliant, and pin-compatible with the 12-bit ADC AD9629 and 10-bit ADC AD9609, enabling easy upgrades from 10-bit and 14-bit converters at sample rates of 20 MSPS to 80 MSPS

• Communications
• Diversity radio systems
• Multi-mode digital receivers: GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
• Smart antenna systems
• Battery-powered instrumentation
• Handheld oscilloscopes
• Portable medical imaging
• Ultrasound
• Radar/LIDAR