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TI SN74ACT74DRRoHS

Manufacturer
MPN
SN74ACT74DR
LCSC Part #
C6933
Packaging
SOIC-14
Customer #
Key Attributes
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
Datasheetpdf iconTI SN74ACT74DR
In-Stock: 1,675
1,675 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
5+$ 0.4439$ 2.22
50+$ 0.3453$ 17.27
150+$ 0.3031$ 45.47
500+$ 0.2448$ 122.40
2,500+$ 0.2213$ 553.25
5,000+$ 0.2072$ 1036.00
Standard Packaging2500/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Flip Flops
ManufacturerTI
PackagingSOIC-14
Operating Temperature-40℃~+85℃
Voltage - Supply4.5V~5.5V
Number of Bits per Element1
Series74ACT Series
Output TypeComplementary type
Number of Elements2
Current - Output High(IOH)24mA
Current - Output Low(IOL)24mA
Setup Time3.5ns
Quiescent Current2uA
Hold Time1ns
Propagation Delay7.5ns@5V,50pF
Trigger TypeRising Edge

Additional Information

TypeDetails
Minimum5
Multiple5
Standard Packaging2500
Sales UnitPiece

Introduction

AI Translation

The 'ACT74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE(overline)) or clear (CLR(overline)) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE(overline) and CLR(overline) are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.

Features

AI Translation
  • 4.5 - 5.5 V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 10.5 ns at 5 V
  • Inputs Are TTL-Voltage Compatible