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Nexperia 74LVC1G08GV-Q100,1 product image
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Nexperia 74LVC1G08GV-Q100,1RoHS

Manufacturer
Nexperia
MPN
74LVC1G08GV-Q100,1
LCSC Part #
C6708307
Packaging
SC-74A
Customer #
Key Attributes
Single 2-input AND gate
Datasheetpdf iconNexperia 74LVC1G08GV-Q100,1
In-Stock: 2,975
2,975 In stock, ships now
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QtyUnit PriceTotal Amount
5+$ 0.1098$ 0.55
50+$ 0.0866$ 4.33
150+$ 0.0749$ 11.24
500+$ 0.0662$ 33.10
3,000+$ 0.0592$ 177.60
6,000+$ 0.0558$ 334.80
Standard Packaging3000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters
ManufacturerNexperia
PackagingSC-74A
Logic Family74LVC Series
Voltage - Supply1.65V~5.5V
Output Logic Level - Low450mV;800mV
Propagation Delay5.5ns@5.5V,50pF
FeaturesLocal shutdown mode;Overvoltage-tolerant input
Input Logic Level - Low700mV~800mV
Operating Temperature-40℃~+125℃
Input Logic Level - High1.7V~2V
Output Logic Level - High2V;3.4V
Quiescent Current(Iq)4uA
Number of Channels1;2
Current - Output High(IOH)24mA
Current - Output Low(IOL)32mA
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Additional Information

TypeDetails
Minimum5
Multiple5
Standard Packaging3000
Sales UnitPiece

Introduction

AI Translation

The 74LVC1G08-Q100 is a single 2-input AND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The l(OFF) circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features

AI Translation
  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 1.65 V to 5.5 V
  • High noise immunity
  • ±24 mA output drive (V(CC)=3.0 V)
  • CMOS low power dissipation
  • Direct interface with TTL levels
  • Overvoltage tolerant inputs to 5.5 V
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance ≤250 mA
  • Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V)
  • ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V