ADI ADSP-BF592KCPZ-2

The ADSP- BF592 processor is a member of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual- MAC state- of- the- art signal processing engine, the advantages of a clean, orthogonal RISC- like microprocessor instruction set, and single- instruction, multiple- data (SIMD) multimedia capabilities into a single instruction- set architecture. The ADSP- BF592 processor is completely code compatible with other Blackfin processors. The ADSP- BF592 processor offers performance up to 400 MHz and reduced static power consumption. By integrating a rich set of industry- leading system peripherals and memory, Blackfin processors are the platform of choice for next- generation applications that require RISC- like programmability, multimedia support, and leading- edge signal processing in one integrated package. The ADSP- BF592 processor is a highly integrated system- on- a- chip solution for the next generation of digital communication and consumer multimedia applications. By combining industry standard interfaces with a high performance signal processing core, cost- effective applications can be developed quickly, without the need for costly external components.

• Up to 400 MHz high performance Blackfin processor
• Two 16- bit MACs, two 40- bit ALUs, four 8- bit video ALUs, 40- bit shifter
• RISC- like register and instruction model for ease of programming and compiler- friendly support
• Advanced debug, trace, and performance monitoring
• Accepts a wide range of supply voltages for internal and I/O operations
• Off- chip voltage regulator interface
• 64- lead (9 mm × 9 mm) LFCSP package
• 68K bytes of core- accessible memory
• 64K byte L1 instruction ROM
• Flexible booting options from internal L1 ROM and SPI memory or from host devices including SPI, PPI, and UART
• Memory management unit providing memory protection
• Four 32- bit timers/counters, three with PWM support
• 2 dual- channel, full- duplex synchronous serial ports (SPORT), supporting eight stereo I'S channels
• 2 serial peripheral interface (SPI) compatible ports
• 1 UART with IrDA support
• Parallel peripheral interface (PPI), supporting ITU- R 656 video data formats
• 2- wire interface (TWI) controller
• 9 peripheral DMAs
• 2 memory- to- memory DMA channels
• Event handler with 28 interrupt inputs
• 32 general- purpose I/Os (GPIOs), with programmable hysteresis
• Debug/JTAG interface
• On- chip PLL capable of frequency multiplication