ADI ADSP-2191MKSTZ-160

The ADSP-2191M DSP is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2191M combines the ADSP-219x family base architecture (three computational units, two data address generators, and a program sequencer) with three serial ports, two SPI-compatible ports, one UART port, a DMA controller, three programmable timers, general-purpose Programmable Flag pins, extensive interrupt capabilities, and on-chip program and data memory spaces. The ADSP-2191M architecture is code-compatible with DSPs of the ADSP-218x family. Although the architectures are compatible, the ADSP-2191M architecture has a number of enhancements over the ADSP-218x architecture. The enhancements to computational units, data address generators, and program sequencer make the ADSP-2191M more flexible and even easier to program. Indirect addressing options provide addressing flexibility— premodify with no update, pre- and post-modify by an immediate 8-bit, two’s-complement value and base address registers for easier implementation of circular buffering. The ADSP-2191M integrates 64K words of on-chip memory configured as 32K words (24-bit) of program RAM, and 32K words (16-bit) of data RAM. Power-down circuitry is also provided to reduce power consumption. The ADSP-2191M is available in 144-lead LQFP and 144-ball mini-BGA packages. Fabricated in a high speed, low power, CMOS process, the ADSP-2191M operates with a 6.25 ns instruction cycle time (160 MIPS). All instructions, except single-word instructions, execute in one processor. The ADSP-2191M’s flexible architecture and comprehensive instruction set support multiple operations in parallel. For example, in one processor cycle, the ADSP-2191M can: • Generate an address for the next instruction fetch • Fetch the next instruction • Perform one or two data moves • Update one or two data address pointers • Perform a computational operation

• 6.25 ns Instruction Cycle Time, for up to 160 MIPS Sustained Performance
• ADSP-218x Family Code Compatible with the Same Easy to Use Algebraic Syntax
• Single-Cycle Instruction Execution
• Single-Cycle Context Switch between Two Sets of Computation and Memory Instructions
• Instruction Cache Allows Dual Operand Fetches in Every Instruction Cycle
• Multifunction Instructions
• Pipelined Architecture Supports Efficient Code Execution
• Architectural Enhancements for Compiled C and Code Efficiency
• Architectural Enhancements beyond ADSP-218x Family are Supported with Instruction Set Extensions for Added Registers, and Peripherals
• Flexible Power Management with User-Selectable Power-Down and Idle Modes
• 160K Bytes On-Chip RAM Configured as 32K Words 24-Bit Memory RAM and 32K Words 16-Bit Memory RAM
• Dual-Purpose 24-Bit Memory for Both Instruction and Data Storage
• Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units with Dual 40-Bit Accumulators
• Unified Memory Space Allows Flexible Address Generation, Using Two Independent DAG Units
• Powerful Program Sequencer Provides Zero-Overhead Looping and Conditional Instruction Execution
• Enhanced Interrupt Controller Enables Programming of Interrupt Priorities and Nesting Modes
• Host Port with DMA Capability for Glueless 8- or 16-Bit Host Interface
• 16-Bit External Memory Interface for up to 16M Words of Addressable Memory Space
• Three Full-Duplex Multichannel Serial Ports, with Support for H.100 and up to 128 TDM Channels with A-Law and μ -Law Companding Optimized for Telecommunications Systems
• Two SPI-Compatible Ports with DMA Support
• UART Port with DMA Support
• 16 General-Purpose I/O Pins with Integrated Interrupt Support
• Three Programmable Interval Timers with PWM Generation, PWM Capture/Pulsewidth Measurement, and External Event Counter Capabilities
• Up to 11 DMA Channels Can Be Active at Any Given Time for High I/O Throughput
• On-Chip Boot ROM for Automatic Booting from External 8- or 16-Bit Host Device, SPI ROM, or UART with Autobaud Detection
• Programmable PLL Supports to 32× Input Frequency Multiplication and Can Be Altered during Runtime
• IEEE JTAG Standard 1149.1 Test Access Port Supports On-Chip Emulation and System Debugging
• 2.5V Internal Operation and 3.3 V I/O
• 144-Lead LQFP and 144-Ball Mini-BGA Packages