ADI ADF7023BCPZ

The ADF7023 is an ultralow power, high performance, highly integrated 2FSK/GFSK/OOK/MSK/GMSK transceiver operating in the 862 MHz to 928 MHz and 431 MHz to 464 MHz bands, covering the license-free 433 MHz, 868 MHz, and 915 MHz ISM bands. It is suitable for circuit applications under European ETSI EN300-220, North American FCC (Part 15), Chinese short-range wireless regulatory standards, or other similar regional standards. Data rates from 1 kbps to 300 kbps are supported. The transmit RF frequency synthesizer incorporates a VCO and a low noise fractional-N PLL with an output channel frequency resolution of 400 Hz. The VCO operates at 2× or 4× the fundamental frequency to reduce spurious emissions. The bandwidths of the receive and transmit frequency synthesizers are automatically and independently configured to achieve optimal phase noise, modulation quality, and settling time. The transmitter output power is programmable from −20 dBm to +13.5 dBm, and automatic PA ramping capability meets transient spurious performance requirements. The device features both single-ended and differential PA outputs, supporting transmit antenna diversity. The receiver offers excellent linearity, with IP3 of −12.2 dBm and −11.5 dBm at maximum and minimum gain respectively, and IP2 of 18.5 dBm and 27 dBm. Receiver blocking performance is 66 dB at ±2 MHz offset and 74 dB at ±10 MHz offset. As a result, the device exhibits outstanding immunity to interfering signals in spectrally noisy environments. The receiver employs a novel high-speed automatic frequency control (AFC) loop, enabling the PLL to detect and correct any RF frequency errors in the recovered data packets. An image rejection calibration scheme, patent pending, is available via firmware download. The algorithm requires no external RF source and no user intervention after startup. Calibration results can be stored in nonvolatile memory for use by the transceiver on subsequent power-ups. The ADF7023 operates from a supply voltage of 2.2 V to 3.6 V with very low power consumption in both Tx and Rx modes, enabling battery-powered systems to operate for extended periods while maintaining excellent RF performance. The device can enter a low power sleep mode in which configuration settings are retained in BBRAM. The ADF7023 features an ultralow power on-chip 8-bit RISC communications processor for radio control, packet management, and smart wake-up mode (SWM) functions. The communications processor integrates the lower layers of a typical communications protocol stack, reducing the processing burden on the host processor. The communications processor also enables downloading and execution of a set of firmware modules, including image rejection (IR) calibration, AES encryption, and Reed Solomon coding. The communications processor provides the host processor with a simple command-based radio control interface. Single-byte commands can transition the radio between states or execute radio functions. The communications processor supports a general packet format. The packet format is highly flexible and fully programmable, ensuring compatibility with proprietary packet definitions. In transmit mode, the communications processor can be configured to append preamble, sync word, and CRC to payload data stored in packet RAM. In receive mode, the communications processor can detect and interrupt the host processor upon receipt of preamble, sync word, address, and CRC, and store the received payload in packet RAM. The ADF7023 employs an efficient interrupt system consisting of independently configurable MAC-level and PHY-level interrupts. Payload data plus 16-bit CRC can be encoded/decoded using Manchester or 8b/10b encoding, or data whitening and de-whitening can be applied. Smart wake-up mode (SWM) allows the ADF7023 to autonomously wake from sleep using an internal wake-up clock without host processor intervention. After waking, the ADF7023 is controlled by the communications processor. This feature enables carrier detection, packet sniffing, and packet reception while the host processor is asleep, thereby reducing overall system power consumption. SWM can wake the host processor based on configurable interrupt conditions. These interrupt conditions can be configured to include reception of valid preamble, sync word, CRC, or address match. Wake-up from sleep can also be triggered by the host processor. For systems requiring highly accurate wake-up timing, a 32 kHz oscillator can be used to drive the wake-up timer. Alternatively, an internal RC oscillator may be used, which offers lower power consumption in sleep mode. The ADF7023 features a hardware-accelerated Advanced Encryption Standard (AES) engine providing 128-bit block encryption and decryption with key sizes of 128 bits, 192 bits, and 256 bits. Both Electronic Codebook (ECB) and Cipher Block Chaining Mode 1 (CBC Mode 1) are supported. The AES engine can be used to encrypt/decrypt packet data and can also function as a standalone engine for host processor encryption/decryption. After downloading the AES software module to program RAM, the ADF7023 enables the AES engine. The AES software module is available from Analog Devices. The on-chip 8-bit ADC can read back external analog inputs, the RSSI signal, or the integrated temperature sensor output. Once the battery voltage drops below a user-defined threshold, the integrated battery voltage monitor asserts an interrupt flag to the host processor.