ADI AD9571ACPZPEC

The AD9571 provides a multioutput clock generator function comprising a dedicated PLL core that is optimized for Ethernet line card applications. The integer-N PLL design is based on a proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), and a preprogrammed feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to 156.25 MHz can be locked to the input reference. Each output divider and feedback divider ratio is preprogrammed for the required output rates. No external loop filter components are required, thus conserving valuable design time and board space. The AD9571 is available in a 40-lead 6mm×6mm lead frame chip scale package and can be operated from a single 3.3V supply. The operating temperature range is -40°C to +85°C

• Fully integrated VCO/PLL core
• 0.17 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
• 0.41 ps rms jitter from 12 kHz to 20 MHz at 125 MHz
• Input crystal or clock frequency of 25 MHz
• Preset divide ratios for 156.25 MHz, 33.33 MHz, 100 MHz, and 125 MHz
• Choice of LVPECL or LVDS output format
• Integrated loop filter
• 6 copies of reference clock output
• Rates configured via strapping pins
• Space saving 6mm×6mm 40-lead LFCSP
• 0.48 W power dissipation (LVDS operation)
• 0.69 W power dissipation (LVPECL operation)
• 3.3V operation

• Ethernet line cards, switches, and routers
• SCSI, SATA, and PCI-express
• PCI support included
• Low jitter, low phase noise clock generation