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ADI AD9544BCPZ
| Manufacturer | |
| MPN | AD9544BCPZ |
| LCSC Part # | C653560 |
| Packaging | LFCSP-48(7x7) |
| Customer # | |
| Key Attributes | Quad Input, 10-Output, Dual DPLL Devices, 1 pps Synchronizer and Jitter Cleaner |
| Datasheet |  ADI AD9544BCPZ |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | ADI | |
| Packaging | LFCSP-48(7x7) | |
| Operating Temperature | -40℃~+85℃ | |
| Output Frequency(Max) | 500MHz | |
| Voltage - Supply | 1.71V~1.89V | |
| Features | Automatic clock switching;Programmable phase and delay control;Output synchronization;Built-in clock monitoring and loss-of-lock detection;Temperature compensation;Network synchronizer clock;On-chip non-volatile parameter storage;Fail-hold | |
| Output Level | CML;HCSL | |
| Number of Outputs | 10 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 260 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
AI Translation
The 10 clock outputs of the AD9544 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail. The AD9544 is available in a 48-lead LFCSP (7mm x 7mm) package and operates over the -40°C to +85°C temperature range.
Features
AI Translation
- Dual DPLL synchronizes 1 Hz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy references
- Complies with ITU-T G.8262 and Telcordia GR-253
- Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, and G.825
- Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb
- Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulus
- Programmable digital loop filter bandwidth: 10^-4 Hz to 1850 Hz
- Automatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operation
- Programmable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported
- 5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)
- 2 differential or 4 single-ended input references
- Crosspoint mux interconnects reference inputs to PLLs
- Supports embedded (modulated) input/output clock signals
- Fast DPLL locking modes
- Provides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXO
- External EEPROM support for autonomous initialization
- Single 1.8 V power supply operation with internal regulation
- Built in temperature monitor/alarm and temperature compensation for enhanced zero delay performance
Applications
AI Translation
- SyncE and GPS synchronization and jitter cleanup
- Optical transport networks (OTN), SDH, and macro and small cell base stations
- OTN mapping/demapping with jitter cleaning
- Small base station clocking, including baseband and radio
- Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
- JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
- Cable infrastructures
- Carrier Ethernet
In-Stock: 10
10 In stock, ships now
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| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 41.765 | $ 41.77 |
Standard Packaging260/Full Tray | ||
Better price for more quantity?
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | ADI | |
| Packaging | LFCSP-48(7x7) | |
| Operating Temperature | -40℃~+85℃ | |
| Output Frequency(Max) | 500MHz | |
| Voltage - Supply | 1.71V~1.89V | |
| Features | Automatic clock switching;Programmable phase and delay control;Output synchronization;Built-in clock monitoring and loss-of-lock detection;Temperature compensation;Network synchronizer clock;On-chip non-volatile parameter storage;Fail-hold | |
| Output Level | CML;HCSL | |
| Number of Outputs | 10 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 260 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
AI Translation
The 10 clock outputs of the AD9544 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail. The AD9544 is available in a 48-lead LFCSP (7mm x 7mm) package and operates over the -40°C to +85°C temperature range.
Features
AI Translation
- Dual DPLL synchronizes 1 Hz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy references
- Complies with ITU-T G.8262 and Telcordia GR-253
- Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, and G.825
- Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb
- Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulus
- Programmable digital loop filter bandwidth: 10^-4 Hz to 1850 Hz
- Automatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operation
- Programmable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported
- 5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)
- 2 differential or 4 single-ended input references
- Crosspoint mux interconnects reference inputs to PLLs
- Supports embedded (modulated) input/output clock signals
- Fast DPLL locking modes
- Provides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXO
- External EEPROM support for autonomous initialization
- Single 1.8 V power supply operation with internal regulation
- Built in temperature monitor/alarm and temperature compensation for enhanced zero delay performance
Applications
AI Translation
- SyncE and GPS synchronization and jitter cleanup
- Optical transport networks (OTN), SDH, and macro and small cell base stations
- OTN mapping/demapping with jitter cleaning
- Small base station clocking, including baseband and radio
- Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
- JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
- Cable infrastructures
- Carrier Ethernet
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |