ADI AD9484BCPZ-500
| Manufacturer | |
| MPN | AD9484BCPZ-500 |
| LCSC Part # | C653480 |
| Packaging | LFCSP-56(8x8) |
| Customer # | |
| Key Attributes | 8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Manufacturer | ADI | |
| Packaging | LFCSP-56(8x8) | |
| Operating Temperature | -40℃~+85℃ | |
| Clock Frequency | 500MHz | |
| Features | Input buffer;Soft reset | |
| Voltage Reference | Built-in | |
| Interface | LVDS | |
| Resolution(Bits) | 8;500MHz | |
| S/N Ratio | 47dB | |
| Voltage - Supply | 1.8V | |
| Number of Channels | 1 | |
| Integral non - linearity | 0.1LSB | |
| Programmable Gain | Support |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 260 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The AD9484 is an 8-bit, monolithic, sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. The VREF pin can be used to monitor the internal reference or provide an external voltage reference (external reference mode must be enabled through the SPI port). The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced BiCMOS process, the AD9484 is available in a 56-lead LFCSP, and is specified over the industrial temperature range ( -40°C to +85°C).
Features
- SNR = 47 dBFS at fIN up to 250 MHz at 500 MSPS
- ENOB of 7.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
- ΔFDR = 79 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
- Integrated input buffer
- Excellent linearity DNL = ±0.7 LSB typical, INL = ±0.7 LSB typical
- LVDS at 500 MSPS (ANSI-644 levels)
- 1 GHz full power analog bandwidth
- On-chip reference, no external decoupling required
- Low power dissipation 670 mW at 500 MSPS—LVDS SDR output
- Programmable (nominal) input voltage range 1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal
- 1.8 V analog and digital supply operation
- Selectable output data format (offset binary, twos complement, Gray code)
- Clock duty cycle stabilizer
- Integrated data capture clock
Applications
- Wireless and wired broadband communications
- Cable reverse path
- Communications test equipment
- Low cost digital oscilloscopes
- Power amplifier linearization
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 90.968 | $ 90.97 |
| 30+ | $ 86.5044 | $ 2595.13 |
Standard Packaging260/Full Tray | ||
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991C1 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991C1 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

