LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
ADI AD9484BCPZ-500 product image
Images for reference only

ADI AD9484BCPZ-500RoHS

Manufacturer
MPN
AD9484BCPZ-500
LCSC Part #
C653480
Packaging
LFCSP-56(8x8)
Customer #
Key Attributes
8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter
Datasheetpdf iconADI AD9484BCPZ-500

Products Specifications

Show similar products (0) >
TypeDescription
CategoryIntegrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC)
ManufacturerADI
PackagingLFCSP-56(8x8)
Operating Temperature-40℃~+85℃
Clock Frequency500MHz
FeaturesInput buffer;Soft reset
Voltage ReferenceBuilt-in
InterfaceLVDS
Resolution(Bits)8;500MHz
S/N Ratio47dB
Voltage - Supply1.8V
Number of Channels1
Integral non - linearity0.1LSB
Programmable GainSupport

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging260
Sales UnitPiece

Introduction

AI Translation

The AD9484 is an 8-bit, monolithic, sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. The VREF pin can be used to monitor the internal reference or provide an external voltage reference (external reference mode must be enabled through the SPI port). The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced BiCMOS process, the AD9484 is available in a 56-lead LFCSP, and is specified over the industrial temperature range ( -40°C to +85°C).

Features

AI Translation
  • SNR = 47 dBFS at fIN up to 250 MHz at 500 MSPS
  • ENOB of 7.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
  • ΔFDR = 79 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
  • Integrated input buffer
  • Excellent linearity DNL = ±0.7 LSB typical, INL = ±0.7 LSB typical
  • LVDS at 500 MSPS (ANSI-644 levels)
  • 1 GHz full power analog bandwidth
  • On-chip reference, no external decoupling required
  • Low power dissipation 670 mW at 500 MSPS—LVDS SDR output
  • Programmable (nominal) input voltage range 1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal
  • 1.8 V analog and digital supply operation
  • Selectable output data format (offset binary, twos complement, Gray code)
  • Clock duty cycle stabilizer
  • Integrated data capture clock

Applications

AI Translation
  • Wireless and wired broadband communications
  • Cable reverse path
  • Communications test equipment
  • Low cost digital oscilloscopes
  • Power amplifier linearization
Out of Stock
Notify Me
Add to BOM List
QtyUnit Price(Reference Only)Total Amount
1+$ 90.968$ 90.97
30+$ 86.5044$ 2595.13
Standard Packaging260/Full Tray
Better price for more quantity?
$