ADI AD9230BCPZ11-200
| Manufacturer | |
| MPN | AD9230BCPZ11-200 |
| LCSC Part # | C653312 |
| Packaging | LFCSP-56(8x8) |
| Customer # | |
| Key Attributes | SPI 1.7V~1.9V LFCSP-56(8x8) Analog to Digital Converters (ADC) RoHS |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Manufacturer | ADI | |
| Packaging | LFCSP-56(8x8) | |
| Operating Temperature | -40℃~+85℃ | |
| Features | Input buffer;Soft reset | |
| Interface | SPI | |
| Resolution(Bits) | 11;200MHz | |
| Voltage - Supply | 1.7V~1.9V | |
| Number of Channels | 1 | |
| Integral non - linearity | 0.5LSB |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 260 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The AD9230-11 is an 11-bit monolithic sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The product operates at up to a 200 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) amplifier and voltage reference, are included on the chip to provide a complete signal conversion solution. The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced CMOS process, the AD9230-11 is available in a 56-lead lead frame chip scale package, specified over the industrial temperature range -40°C to +85°C.
Features
- SNR = 62.5 dBFS @ fIN up to 70 MHz @ 200 MSPS
- ENOB of 10.2 @ fIN up to 70 MHz @ 200 MSPS (−1.0 dBFS)
- SFDR = -77 dBc @ fIN up to 70 MHz @ 200 MSPS (−1.0 dBFS)
- Excellent linearity: DNL = ±0.15 LSB typical, INL = ±0.5 LSB typical
- LVDS at 200 MSPS (ANSI-644 levels)
- 700 MHz full power analog bandwidth
- On-chip reference, no external decoupling required
- Integrated input buffer and track-and-hold amplifier
- Low power dissipation: 373 mW @ 200 MSPS (LVDS SDR mode), 328 mW @ 200 MSPS (LVDS DDR mode)
- Programmable input voltage range 1.0 V to 1.5 V, 1.25 V nominal
- 1.8 V analog and digital supply operation
- Selectable output data format (offset binary, twos complement, gray code)
- Clock duty cycle stabilizer
- Integrated data capture clock
Applications
- Wireless and wired broadband communications
- Cable reverse path
- Communications test equipment
- Radar and satellite subsystems
- Power amplifier linearization
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 134.2585 | $ 134.26 |
| 260+ | $ 51.9576 | $ 13508.98 |
| 520+ | $ 50.1316 | $ 26068.43 |
| 1,040+ | $ 49.2294 | $ 51198.58 |
Standard Packaging260/Full Tray | ||
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991C2 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991C2 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

