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ADI AD9211BCPZ-200 product image
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ADI AD9211BCPZ-200RoHS

Manufacturer
MPN
AD9211BCPZ-200
LCSC Part #
C653251
Packaging
LFCSP-56(8x8)
Customer #
Key Attributes
LVDS 1.7V~1.9V LFCSP-56(8x8) Analog to Digital Converters (ADC) RoHS
Datasheetpdf iconADI AD9211BCPZ-200

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC)
ManufacturerADI
PackagingLFCSP-56(8x8)
Operating Temperature-40℃~+85℃
FeaturesInput buffer;Soft reset
InterfaceLVDS
Resolution(Bits)200MHz;10
Voltage - Supply1.7V~1.9V
Number of Channels1
Integral non - linearity0.2LSB

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging260
Sales UnitPiece

Introduction

AI Translation

The AD9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution. The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP, specified over the industrial temperature range -40℃ to +85℃.

Features

AI Translation
  • SNR = 60.1 dBFS @ fIN up to 70 MHz @ 300 MSPS
  • ENOB of 9.7 @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS)
  • SFDR = -80 dBc @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS)
  • Excellent linearity DNL = ±0.1 LSB typical INL = ±0.2 LSB typical
  • LVDS at 300 MSPS (ANSI-644 levels)
  • 700 MHz full power analog bandwidth
  • On-chip reference, no external decoupling required
  • Integrated input buffer and track-and-hold
  • Low power dissipation 437 mW @ 300 MSPS—LVDS SDR mode 410 mW @ 300 MSPS—LVDS DDR mode
  • Programmable input voltage range 1.0 V to 1.5 V, 1.25 V nominal
  • 1.8 V analog and digital supply operation
  • Selectable output data format (offset binary, twos complement, Gray code)
  • Clock duty cycle stabilizer
  • Integrated data capture clock

Applications

AI Translation
  • Wireless and wired broadband communications
  • Cable reverse path
  • Communications test equipment
  • Power amplifier linearization
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QtyUnit Price(Reference Only)Total Amount
1+$ 70.7789$ 70.78
260+$ 27.3905$ 7121.53
520+$ 26.4289$ 13743.03
1,040+$ 25.952$ 26990.08
Standard Packaging260/Full Tray
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