SKYWORKS SI5389B-A13501-GM
| Manufacturer | |
| MPN | SI5389B-A13501-GM |
| LCSC Part # | C6488848 |
| Packaging | LGA-64(9x9) |
| Customer # | |
| Key Attributes | 718.5MHz 1 LGA-64(9x9) Clock Generators, PLLs, Frequency Synthesizers RoHS |
| Datasheet |  SKYWORKS SI5389B-A13501-GM |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | SKYWORKS | |
| Packaging | LGA-64(9x9) | |
| Operating Temperature | - | |
| Output Frequency(Max) | 718.5MHz | |
| Voltage - Supply | 1.8V;3.3V | |
| Features | Automatic clock switching;Network synchronizer clock;On-chip non-volatile parameter storage;Built-in clock monitoring and loss-of-lock detection | |
| Output Level | CML;LVPECL;HCSL;LVCMOS;LVDS | |
| Number of Outputs | 1 |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 260 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The multi-DSPLL Si5388/89 network synchronizer clocks combined with optional AccuTime 1588 software offer a complete solution for IEEE 1588v2 and SyncE phase and frequency synchronization. AccuTime 1588 software consists of a servo algorithm internal to the Si5388/89 clock and is paired with a protocol stack that runs on the host processor. The Si5388/89 targets compact or centralized "pizza box" architectures requiring low jitter. The device offers up to three independent DSPLLs, each capable of supporting IEEE 1588 high resolution DCO control, G.8262 SyncE clock filtering, or general-purpose clocking. The unique design of the Si5388/89 includes a dedicated TCXO/OCXO reference interface with built-in jitter cleaning that will not degrade the output performance of the clock. The Si5388/89 supports free-run, synchronous, and holdover modes as well as enhanced hitless switching, minimizing the phase transients associated with switching between input clocks. These devices are programmable via a serial interface with in-circuit programmable non-volatile memory (NVM), so they always power up with a known frequency configuration. Configuring and programming the Si5388/89 is easy with Skyworks’ ClockBuilder Pro software.
Features
- Up to three independent DSPLLs in a single IC supporting SyncE, IEEE 1588 DCO, General Clocking
- Input frequency range:
- Dedicated External crystal input: 48–54 MHz
- Dedicated REF clock input : 5–250 MHz
- 3 Differential clock inputs: 8 kHz–750 MHz
- 2 LVCMOS clocks inputs: 1PPS, 8 kHz– 250 MHz
- Output frequency range:
- 8 Differential outputs: 1 Hz, 100 Hz– 718.5 MHz
- 16 LVCMOS: 1 Hz, 100 Hz–250 MHz
- Ultra-low jitter: 90 fs rms typ
- Enhanced hitless switching minimizes output phase transients
- Dedicated Input and DSPLL for Holdover Reference
- Reference Design Support
- ORAN compliant
- Embedded IEEE 1588 servo loop processing on Si5388/89
- IEEE 1588 software protocol stack runs on host processor
- Unique servo algorithm has statistical packet selection, which dynamically adjusts to changing network load conditions to mitigate PDV effects
Applications
- Telecom Boundary Clock and Telecom-Time Slave Clock (T-BC, T-TSC) ITU-T G.8273.2
- Telecom Boundary Clock for Partial Timing Support (T-BC-P, T-TSC-P) ITU-T G.8273.4
- Synchronous Ethernet (SyncE) ITU-T G.8262 and Enhanced Synchronous Ethernet (eEEC) G.8262.1
- Stratum 3/3E, G.812, G.813 network synchronization
- Frequency synchronization in packet networks ITU-T G.8261
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 132.7448 | $ 132.74 |
| 260+ | $ 52.967 | $ 13771.42 |
| 520+ | $ 51.1969 | $ 26622.39 |
| 1,040+ | $ 50.3224 | $ 52335.30 |
Standard Packaging260/Full Tray | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | SKYWORKS | |
| Packaging | LGA-64(9x9) | |
| Operating Temperature | - | |
| Output Frequency(Max) | 718.5MHz | |
| Voltage - Supply | 1.8V;3.3V | |
| Features | Automatic clock switching;Network synchronizer clock;On-chip non-volatile parameter storage;Built-in clock monitoring and loss-of-lock detection | |
| Output Level | CML;LVPECL;HCSL;LVCMOS;LVDS | |
| Number of Outputs | 1 |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 260 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The multi-DSPLL Si5388/89 network synchronizer clocks combined with optional AccuTime 1588 software offer a complete solution for IEEE 1588v2 and SyncE phase and frequency synchronization. AccuTime 1588 software consists of a servo algorithm internal to the Si5388/89 clock and is paired with a protocol stack that runs on the host processor. The Si5388/89 targets compact or centralized "pizza box" architectures requiring low jitter. The device offers up to three independent DSPLLs, each capable of supporting IEEE 1588 high resolution DCO control, G.8262 SyncE clock filtering, or general-purpose clocking. The unique design of the Si5388/89 includes a dedicated TCXO/OCXO reference interface with built-in jitter cleaning that will not degrade the output performance of the clock. The Si5388/89 supports free-run, synchronous, and holdover modes as well as enhanced hitless switching, minimizing the phase transients associated with switching between input clocks. These devices are programmable via a serial interface with in-circuit programmable non-volatile memory (NVM), so they always power up with a known frequency configuration. Configuring and programming the Si5388/89 is easy with Skyworks’ ClockBuilder Pro software.
Features
- Up to three independent DSPLLs in a single IC supporting SyncE, IEEE 1588 DCO, General Clocking
- Input frequency range:
- Dedicated External crystal input: 48–54 MHz
- Dedicated REF clock input : 5–250 MHz
- 3 Differential clock inputs: 8 kHz–750 MHz
- 2 LVCMOS clocks inputs: 1PPS, 8 kHz– 250 MHz
- Output frequency range:
- 8 Differential outputs: 1 Hz, 100 Hz– 718.5 MHz
- 16 LVCMOS: 1 Hz, 100 Hz–250 MHz
- Ultra-low jitter: 90 fs rms typ
- Enhanced hitless switching minimizes output phase transients
- Dedicated Input and DSPLL for Holdover Reference
- Reference Design Support
- ORAN compliant
- Embedded IEEE 1588 servo loop processing on Si5388/89
- IEEE 1588 software protocol stack runs on host processor
- Unique servo algorithm has statistical packet selection, which dynamically adjusts to changing network load conditions to mitigate PDV effects
Applications
- Telecom Boundary Clock and Telecom-Time Slave Clock (T-BC, T-TSC) ITU-T G.8273.2
- Telecom Boundary Clock for Partial Timing Support (T-BC-P, T-TSC-P) ITU-T G.8273.4
- Synchronous Ethernet (SyncE) ITU-T G.8262 and Enhanced Synchronous Ethernet (eEEC) G.8262.1
- Stratum 3/3E, G.812, G.813 network synchronization
- Frequency synchronization in packet networks ITU-T G.8261
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |